JPS6051334B2 - Maximum demand power control device - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a maximum demand power control device, more specifically,
The present invention relates to a maximum demand power control device that controls the power load side so that the maximum demand power does not exceed contract power.

As a recent trend, there is a movement among electricity consumers to automatically control power consumption to suppress the maximum power demand, thereby saving resources and reducing electricity charges. In order to adapt to this purpose, various maximum demand power control devices have been proposed and implemented.

However, all of the maximum demand power control devices according to existing proposals of this type have the disadvantage that they are difficult to synchronize with the operation of the maximum demand power meter, which is the standard for power trading, and this makes it difficult for power consumers to This has led to various disputes between the company and electricity suppliers.

In view of this conventional situation, the present invention aims to provide a maximum demand power control device that can automatically synchronize with a transaction maximum demand power meter and appropriately and effectively control the load. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the maximum demand power control device according to the present invention will be described in detail below with reference to the accompanying drawings, together with a conventional example. First, an overview of representative maximum demand power control devices according to existing proposals will be described with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram showing an outline of a conventional device.

In FIG. 1, the clock pulse generation circuit 1 outputs control pulse signals φ0, φ1, φ2, φ3 shown in FIG.
is output in a predetermined order and at time intervals, and is set to match the operating time limit of the maximum demand power meter (not shown), which is the calculation standard for power trading. The signal φ that is output first. is given to the comparator circuit 8 as a lock command, and this comparator circuit 8 is connected to the signal φ. It's been a long time since the start of. The device continues to lock until the period of time elapses, preventing its operation. Then, the transaction power meter 2 outputs a power pulse P proportional to the passed power, causes the counting circuit 3 to count the number of pulses, and outputs the thus obtained count value signal S1 to the multiplication circuit 4. do.

Further, the down counter 5 receives the signal φ.

When the value falls and disappears, a calculation is performed to decrease the number by one for each short time Δt, for example, about one minute, which is separately set.
Outputting a signal St such that St=T-t to the multiplication circuit 4,
This multiplier circuit 4 outputs a signal Sa that is the product of the signals St. Subsequently, in the first addition circuit 6, the set time Δt
each time lapses, receives the input of the control pulse signal φ2, adds and stores the output signal S1 of the counting circuit 3, and outputs the sum signal S2 to the second adding circuit 7;
The second addition circuit 7 calculates the sum with the signal Sa from the multiplication circuit 4, and outputs the numerical signal Sb obtained by this calculation to the comparison circuit 8.

Here, the comparison circuit 8 compares the signal Ss predetermined according to the contract power with the numerical signal Sb, and
s<signal Sb, the comparison circuit 8 outputs a cutoff signal to the sequential load control circuit 9, and sequentially commands the sequential load control circuit 9 to cut off non-urgent load lines. This results in a considerable reduction in power demand.

Now, assuming the power load curve shown in FIG. 3, let us consider the state when time t+Δt has elapsed from the initial stage.

The multiplication circuit 4 is supplied with the count value signal S1 of the electric energy pulse P counted by the counting circuit 3 and the remaining time signal St from the down counter 5 for a time Δt, and the multiplication circuit 4 At the moment when the control pulse signal φ1 is input to the circuit 4, the multiplication circuit 4 is operated, and the product signal Sa is outputted to the second addition circuit 7.

The first adding circuit 6 adds and stores the count value signal S1 of the counting circuit 3 every time the control pulse signal φ2 is input, and the value naturally changes in a stepwise manner. , at the moment when the control pulse signal φ1 is input to the multiplication circuit 4 after the above-mentioned time +Δt, this repeatedly added integrated value signal S2 is similarly output to the second addition circuit 7. The output signal Sb of the adder circuit 7 of 2 is given by the following equation. If we look at this with reference to FIG. 3 above, it will be as follows.

That is, the integrated value output S2 of the first adding circuit 6 is
The product output Sa of the multiplier circuit 4 is proportional to the passing electric power P1, and as shown by the dashed line in the same figure, the time T
Since it is proportional to the expected power consumption Pu until
The value is proportional to U.

Then, the comparison circuit 8 compares the contract power Ws and the time limit T.
The allowable power amount Ps obtained as the product of It outputs a signal and sequentially cuts off non-urgent load lines to limit the power demand.

Note that FIG. 3 shows that the non-urgent load is cut off at time t1+Δt, and the demand power is reduced.

Therefore, in the conventional device, each time Δt elapses, the expected amount of power P1+PU is calculated by calculation.
is determined and compared with the allowable power amount Ps to perform maximum demand power control, which has the following drawbacks.

Large amounts of power that are rapidly consumed in a short period of time, such as inrush current in large direct-line motors that have a capacity that is a relatively large proportion of one contract power, may affect the expected amount of power that will be reached, resulting in unnecessary There is a risk of severe load shedding.

Since the time interval (every Δt) between the two comparison and discrimination operations is long, the ability of control to follow rapidly changing power demand is extremely poor, making it difficult to automate restoration input.

3 The operating time limit of the maximum demand power meter for withdrawal and the operating time limit of the device itself are determined by independent time limit circuits, and synchronization between them can only be achieved manually, resulting in large operation errors due to accumulated time limit errors. This causes a time lag, which causes problems between power consumers and power suppliers.

In addition, these drawbacks are that even though there are some differences in the control means, the system uses a method that calculates the expected amount of power to arrive and compares it with the allowable amount of power to control the maximum demand power. The same applies to all control devices.

Next, an outline of an embodiment of the maximum demand power control device according to the present invention, which has a device configuration that improves the drawbacks of the conventional device, will be described with reference to FIGS. 4 to 6.

FIG. 4 is a block configuration diagram showing the outline of this embodiment device, FIGS. 5 and 6 are signal waveform diagrams of the main parts of the device, and FIG. 7 is a load power curve and an operating curve of the device. It is an explanatory diagram.

In FIGS. 4 and 5, the transaction power meter 11 outputs a power pulse P (for example, 300
0 pulses/KWh) is output, and the amount of electricity passing through this trading wattmeter 11 is determined by the input of the trading wattmeter 11,
In other words, it is expressed in units of the secondary side of the transaction transformer.

This electric energy pulse P is then frequency-divided by a predetermined integer ratio (for example, 1/3) by the frequency dividing circuit 12 at the next stage, and the pulse P
a (therefore, 1000 pulses/KWh), and the temporary storage element 12 built in the output side of this frequency dividing circuit 12
After being held at a, it is output as a pulse P,
This pulse P1 is also 1000 pulses/KWhl, in other words, it represents the electric energy of 1 Wh per pulse. The pulse P1 is generated by the shift register 1 at the rising edge of the pulse signal φ1 output from the clock pulse generation circuit 14 at predetermined time intervals Δt (for example, 0.6 seconds).
The number of elements read in is 3, which corresponds to the time period T.
After repeating the shift of 00(2), the pulses are sequentially output from the output end as pulses PlS.

That is, this pulse PlS is in this case a reproduction of the pulse P1 before the time limit T. In addition, as shown in FIG. 6, the temporary storage element 12a is stored in the temporary storage element 12a, as shown in FIG. The divided pulse interval becomes a long waveform, and the wavelength becomes longer than the interval of the pulse signal φ1 output every time Δt (for example, 0 seconds), and the divided pulse output is directly transferred to the shift register 13. If input, this shift register 13 will read multiple single waveforms of frequency-divided pulses each time the pulse signal φ1 is input, so this shift register 13 is provided to avoid this.

That is, this temporary storage element 12a is set at the rising edge of the output of the frequency dividing circuit 12, and is reset at the falling edge of the pulse signal φ1 when reading and shifting into the shift register 13 is completed by the pulse signal φ1. In this way, multiple reading of the frequency-divided pulses is prevented. Both of these pulses Pl, Pl as read and described above
S is inputted to the discriminating circuit 15 at the next stage and compared with each other.
t(a). 6 seconds) unit power pulse (1
Wh) and Δt(a) at the current time. This is a comparison with the presence or absence of a unit power pulse (1Wh) within a period of time (6 seconds). That is, as a result of the comparison operation in the discriminating circuit 15, if both pulses Pl and PlS are present at this time, then in this case, the pulse P will be changed at exactly the interval of time T (3 times).
1 has been output, and this time period T (3 times) is divided into time intervals Δt (a). 2), there is no increase or decrease in the number of pulses P1 within this time, in other words, it means that there is no change in the average power demand at the moment.
This also applies to the case where both pulses Pl and PlS do not exist, and no determination result is output for each.

However, on the other hand, if within Δt (0 seconds) time, "Pulse P1 exists and pulse PlS does not exist", this means that the time period T (3 times) is changed by the time interval Δt (05 seconds). When shifted, it is determined that the number of pulses P1 within this time increases, in other words, the average power demand at the present time is on an increasing trend compared to before time limit T, and outputs an increasing pulse signal Pu. do.

For example, if the shift register 13 is Δt(a). While repeating the time shift 30 (4) times (6 seconds), pulse P1 becomes NR.
Assuming that this 500W measurement state continues after starting from the starting state, which is OJ, the signal RL does not appear at the output PlS of the shift register 13 for the first three cycles, but the pulse of Therefore, the discriminating circuit 15 detects the state of 250 quotient, and the rising i
The counting circuit 16 receives the signal Pu from the discrimination circuit 15 and counts R25O.

At this point, if we reread the counting output of the up/down counting circuit 16 in units of 2 W, we can read that the average power demand within the previous measurement time period T1 was 500 W.

For example, if the power demand becomes zero after 3C@ and 6 minutes have passed since then, the input P1 will be held at the signal ROJ for these 8 minutes, and the signal r1 will appear at the output PLS. The discrimination circuit 15 detects the state of and outputs the signal Pu, and the count value of the up/down counter circuit 16 becomes R2.
On the other hand, the average power demand within the measurement time period T, which goes back to that point, is equal to the count value of the up/down counter circuit 16 in the previous equation.

Next, as a second specific example, for example, if the average demand power is 50
If 0W continues for a long time, changes to 1000W at a certain point, and 15 minutes have passed, the count value of the up/down counter circuit 16 at 500W before the change is R25OJ, and the output PlS outputs the signal 11 during the following one period. The total number of times when this will appear is Rl25J.
In addition, the number of outputs of the signal RlJ to the input P1 at 1000 W is, so the difference between the number of outputs of the signal Pd and the output is as follows.

Therefore, after the power demand has increased, the count value of the lift counting circuit 16 after one conflict has increased from R25OJ at the time of change to R25OJ, which, as before, indicates the average power demand, Here again, the average power demand within the measurement time period T, 3, which goes back to that point in time, matches the count value of the up/down counter circuit 16 in the previous equation.

In this way, in the up/down counting circuit 16, the discrimination circuit 15
The counting operation is performed for the rising and falling pulse signals Pu and Pd outputted from the rising pulse signal Pu, and counting is performed as a count-up when the rising pulse signal Pu is input, and as a count-down when the falling pulse signal Pd is input. As is clear from Fig. 5, the configuration is configured so that it operates for the first time only when the same type of pulse signal arrives two or more times in succession, and these two signals Pu and Pd are repeatedly output alternately, and the average demand Even when there is no large change in the power, the count value of the lift counting circuit 16 is prevented from frequently rising or falling by RlJ, and with this configuration, the lift counting circuit 16 has a negative error of 1 digit only when rising. However, this can be compensated for by negative correction of the setting signal S to the comparison circuit 17, which will be described below, by one digit.

That is, as a result of such an operation in the up/down counting circuit 16, the circuit 16 outputs the counting signal S as the average power demand within the time limit T (3 times).

It will be output as In other words, both signals Pu and Pd input to this up/down counting circuit 16 are
It is related to the passing power pulse P output from 1,
Each pulse means a predetermined power shadow KWh. For example, if N pulses are input every time period T, AN(KWh)
The average power demand within the same time limit T is expressed as .
The count signal S is input to the next-stage comparison circuits 17 and 18, respectively.

These comparison circuits 17 and 18 have a setting upper limit value SHl corresponding to β1 times the contracted power in circuit 17 and a setting lower limit value corresponding to β2 times the contracted power in circuit 18, as shown in FIG. SL is input, comparison circuit 1
In step 7, the input count signal SO is compared with the set upper limit value SH, and the count signal S is output. exceeds the set upper limit SH, the sequential load control circuit 19 is activated on the condition that the rising pulse signal Pu from the discrimination circuit 15 is input, in other words, the demand power is still increasing.
The comparator circuit 18 outputs a cutoff signal to cut off the non-urgent loads in order of frequency of use. The set lower limit β1 is compared with the number signal S.
is below the set lower limit value S, the sequential load A closing signal is output to the control circuit 19, and a closing operation is performed for the current cut-off recovery or cut-off loads in order of frequency of use. That is, in this way, as shown in FIG. 7, the measured value S.

The demand power PO corresponding to the contract power allowable power P
At the time ζ or T4 when the power amount PH of the upper limit value SH corresponding to s is reached, the non-urgent load is cut off, and at the time when the power amount PL of the lower limit value SL is reached, the cut-off is restored and the timer is turned on. As a result, the demand power PO will vary from the upper limit of the power amount PH to the lower limit of the allowable power amount Ps set in advance by the contract power. It will be automatically controlled within the range up to PL. As described in detail above, in accordance with the present invention, unlike the intermittent measuring means in the conventional device, the integration is performed in the same manner as in the conventional device from the time the power is turned on until the first measurement time period T elapses. Measurement is performed, but after the measurement time limit T has elapsed, the minute time Δ
Since the measurement time is shifted every within t and the current power demand is always compared with the power demand before the measurement time T, synchronization can be achieved with an error within a minute time Δt. As a result, the average power demand is determined and controlled every minute time Δt, which has the advantage of quick response speed.Also, since the power demand is compared within the measurement time period T, the power demand can be compared quickly. The influence of time load is extremely small,
Moreover, in order to make the determination while shifting by minute time Δt, it can be automatically synchronized with the maximum demand power meter for transactions.
It has various excellent features.

[Brief explanation of drawings]

Fig. 1 is a block configuration diagram showing an overview of a conventional maximum demand power control device, Fig. 2 is a timing chart of control signals of the above device, and Fig. 3 is an explanatory diagram showing the load power curve and operating curve of the above device. FIG. 4 is a block configuration diagram showing an overview of an embodiment of the maximum demand power control device according to the present invention, FIGS. 5 and 6 are signal waveform diagrams of the main parts of the same device, and FIG. It is an explanatory view showing a load power curve and an operation curve of the device same as the above. 11... Energy meter for transaction, 12... Frequency dividing circuit, 12a... Temporary storage element, 13...
... Uft register, 14 ... Clock pulse generation circuit, 15 ... Discrimination circuit, 16 ... Up/down counting circuit, 17, 18 ... Comparison circuit, 19 ...
- Sequential load control circuit.

Claims (1)

[Claims] 1. Input the passing power demand P from the transaction electricity meter,
A frequency dividing circuit that obtains a number of pulse signals P_1 proportional to the amount of passed electricity demand P, holds this pulse signal P_1 in a temporary storage element and outputs it, and inputs the pulse signal P_1 every minute time Δt, A shift register that outputs a pulse signal P_1s after the measurement time T of the maximum demand wattmeter has elapsed, and a shift register that outputs the pulse signal P_1 and the pulse signal P_1.
If the pulse signal P_1s is not input when the pulse signal P_1 is input, the rising pulse P
a determination circuit that outputs a falling pulse signal Pd when the pulse signal P_1 is not input when the pulse signal P_1s is input, and determines an increase or decrease in the average power demand;
an up/down counting circuit that relatively calculates the rising pulse Pu and the falling pulse signal Pd and outputs the average demand power amount within the measurement time period T as a measurement value signal S_0; Upper limit and lower limit power amount signal P_
Comparing the signals P_H and S_0 with respect to H・P_L under the condition that the rising pulse Pu is input, the signal S_0 is P_H.
When the signal S_0 exceeds P_L, a cutoff signal is output to the sequential load control circuit, and when the signal P_L and S_0 are compared with each other under the input of the falling pulse signal Pd, when the signal S_0 becomes below P_L, a cutoff signal is output to the sequential load control circuit. 1. A maximum demand power control device, comprising: a comparison circuit that outputs a power-on signal, and is configured to constantly maintain average power demand within a range between an upper limit and a lower limit power amount. 2. Claim 1, characterized in that when a predetermined number of rising and falling pulses Pu, Pd are input, the rising/falling counting circuit outputs the measured value signal S_0 of the average demand power amount. Maximum demand power control device.