JPS6051298B2 - Automatic speed switching method and device for facsimile receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication speed switching method and device for a facsimile receiver.

Facsimile communications are generally carried out over telephone lines;
High-speed transmission and reception is possible when the transmission frequency band of the circuit is relatively wide, but when a narrow-band line must also be used, the image quality will deteriorate unless the communication speed is lowered, which does not meet practical requirements. It becomes unsatisfactory.

Therefore, facsimile transmitters and receivers are required to switch communication speeds according to the characteristics of the lines in use, and conventionally the following methods have generally been used.

That is, the transmitter and the receiver are provided with a changeover switch, and the operators of both parties manually switch according to a prior arrangement, or the transmitter sends out a tone signal of a specific frequency corresponding to the communication speed. Means for receiving and selecting these tone signals in a receiver and automatically switching the communication speed has been put into practice.

However, in the former case, manual operation is always required and operation errors are likely to occur; in the latter case, it is natural that noise mixed into the line may occur due to incorrect connection, and if the communication voice contains the same frequency component as the tone signal. If a malfunction occurs and communication is performed without realizing it, the speeds of the transmitter and receiver will differ, making it impossible to obtain the desired received image, which may unnecessarily cause loss of consumables such as reception recording paper and wear and tear on the device. This results in
Furthermore, when tone signals are used, the receiver requires a high-selectivity transducer, which requires the use of a fairly expensive transducer, making the device expensive. There has been a desire for an automatic communication speed switching method that can operate reliably. Therefore, the present invention solves all of these conventional deficiencies at once, and provides a facsimile receiver that detects the period of the phase signal arriving from the facsimile transmitter and automatically switches the communication speed. of a predetermined period based on the input signal of ! a first time gate that generates a pulse signal and has a time width that includes two or more regular phase signals by the pulse signal; and a second time gate that has a time width that includes more regular phase signals than the first time gate. and detecting whether the number of pulses/signals of the predetermined period is normal during a first time gate period, and counting the number of pulse signals of the predetermined period during a second time gate period. The frequency of the local synchronization signal that controls the operation of the facsimile receiver is set in accordance with the result of counting the number of pulses during the second time gate period only when the detection result is normal, thereby ensuring operation. The present invention also provides an automatic speed switching method and device for a facsimile receiver that can be configured at low cost.

Hereinafter, details will be explained with reference to figures showing embodiments of the present invention.

Fig. 1 is a block diagram showing a schematic configuration of the present invention, Fig. 2 shows a phase signal sent from a transmitter for the purpose of maintaining synchronous operation, and Fig. 3 shows Fig. 1 in more detail. FIG. 2 is a block diagram of a circuit embodied in FIG.

FIG. 4 and subsequent figures are time charts of signal waveforms corresponding to each part of FIGS. 1 and 3, and are given the same symbols.
In FIG. 1, IN is an input terminal connected to a phase signal detection circuit of a facsimile receiver, to which a phase signal sent from a transmitter is applied.

As an example, it is assumed that one of the two types of phase signals, high speed and low speed, is transmitted, and in the case of high speed, the phase signal shown in Fig. 2 a1
If the speed is low, the signal A2 in FIG. 2 is applied to the input terminal 1N. It should be noted that the phase signal has a certain relationship at both high and low speeds, and here, the phase signal period at low speed? 1.5 of the phase signal period TPl when P2 is high speed
The explanation will proceed assuming that there is a relationship f8, that is, TP2=1.5Tp1. In addition, XG in Fig. 1 is a stable oscillator with a constant oscillation frequency, such as a crystal oscillator, and the output of this is divided by a frequency divider DV to obtain a local synchronization signal SY that controls the receiver operation. By varying the frequency division ratio of this frequency divider DV, a local synchronization signal SY with a period corresponding to the communication speed determined based on the received phase signal is generated.
It has become a common occurrence. Therefore, in this method, it is necessary to send only a phase signal from the transmitter before starting communication, and the communication speed of the receiver is automatically switched and set accordingly. Ru.
Now, if the phase signal A2 in FIG. 2 is sent out from the transmitter, the signal shown in A2 in FIG. 4 is applied to the input terminal as an input signal. Note that the shaded area in A2 of FIG. 4 is a noise component mixed in the line. The PG in Fig. 1 is a pulse generator that generates a pulse signal of a predetermined period only when the input signal continues for a certain period of time or more, and can be easily obtained by combining a blocking oscillator and an integrating circuit. It can be easily constructed by using a transistor or the like.

As shown in FIG. 4b, the pulse generator PG does not immediately generate a pulse even when an input signal arrives. A pulse is generated only when the input signal continues for a certain period of time, and the input signal S
1, a pulse of Kg is generated and this is attempted to be continued at a predetermined period, but the operation is stopped when the input signal S1 ends. However, since the duration of noise component N1 is long, B2,
Generate two pulses b3. Further, like the noise component N3, if the duration is less than a certain time width, there is no response and no pulse is generated. Therefore, the regular phase signal S1
-S7 etc., one pulse is always generated, but for irregular input signals, no pulse is generated, or an indefinite number of pulses are generated. The pulse signal generated in this manner is transmitted to a first gate pulse generator GGl which generates a gate pulse for setting a first time gate having a time width including two or more regular phase signals.
is driven to generate the gate pulse shown in Fig. 4.

The time width ml of this gate pulse is narrower than the time width obtained by subtracting the signal pulse width b from two periods of the high-speed phase signal shown in FIG. 2, and at the same time wider than one period of the low-speed phase signal, that is, The relationship is set as (liver p1-TO)≧ml>TP2. Therefore, if the phase signal is normal, a gate pulse with a time width including two signals is always generated for both high and low speeds. Also, a second gate pulse is generated to generate a gate pulse for setting a second time gate using the complementary output of the first gate pulse generator GGl shown in FIG. phantom is also driven, producing the gate pulse shown in FIG. 4 E2, the pulse width Te of which is
It is set to include more regular phase signals than the time gate, and in this case, (4TP1-TO) ≧beats> liver P2
It is set in relation to

It is to be noted that each gate pulse generator Gq, GG2 may be a monostable multivibrator or the like, with the time constant appropriately selected. The output of the first gate pulse generator Gq controls the binary counter CTl and puts it into the operating state. Therefore, the binary counter CTl counts the number of output pulses of the pulse generator PG, and the counted value becomes 2. When the voltage is low, an output is generated and this state is maintained during the period in which the output of the first gate pulse generator Gq is present.

This is shown in FIG. 4h. The output of the second gate pulse generator GG2 controls the counter CT2 via a logic judgment circuit, and as a general rule, the counter CT2 is controlled during the gate pulse period from the second gate pulse generator GG2.
2 performs a counting operation, and the output of the pulse generator PG and the output of the binary counter CTl are given to the logic judgment circuit 2, and the output pulse of the first gate pulse generator VJl corresponding to the first time gate. It is detected whether the output pulses of the pulse generator PG during the period are regular or not, that is, the number of pulses is counted. If it is determined that the output pulses are irregular, the output of the second gate pulse generator GG2 is blocked and the counter CT2 is is now being reset. Therefore, only when the pulse signal from the pulse generator PG during the first time gate period is normal, the counter CT2 counts the pulse signal during the second time gate period and outputs an output based on the counting result. to the drive circuit DR, and the drive circuit D
R is a relay R that starts the frequency divider DV and the image receiving section
L is controlled to complete the receiving state at a speed corresponding to the phase signal given as the input signal. In addition, each counter C
Tl and CT2 may be configured by a combination of flip-flop circuits, etc. Similarly, the frequency divider D■ may be a combination of a required number of high-speed responsive flip-flop circuits, etc., and the number of frequency division stages may be changed according to the output of the drive circuit DR. This can be easily achieved by the following means.

The operation of the present invention is as described above, and FIG.
, b, dl, h, the noise components Nl, N2
For the phase signals S1 to S3 when mixed with the phase signals S4 to S7 when normally received, the binary counter CT
Since the timings at which the output h of l is generated are different, and based on this it is possible to determine whether the input signal is normal or not, there is no risk of malfunction due to noise components Nl, N2, etc. Even when a signal is missing, no misunderstanding occurs.

Further, the pulse l generator PG does not respond to short-time noise components such as the noise component N3, and this also prevents misidentification and malfunction from occurring. The specific circuit configuration based on the above outline is shown in Figure 3, and the frequency divider DV in Figure 1 is divided into a variable frequency divider and a fixed frequency divider FD in more detail. It has been done.

Now, if the local synchronization signal is set to 15 Hz at high speed and 10 Hz at low speed in accordance with the phase signal shown in Fig. 2, oscillator XG
The oscillation frequency of the variable frequency divider MD is set to 2304 KHz, the frequency division ratio of the variable frequency divider MD is selected to 112 or 113, and the frequency division ratio of the fixed frequency divider FD is selected to 1176800. It can be easily constructed by using frequency dividing circuits 6, 1110, 1110, and 114 in series. That is, if the frequency division ratio of the variable frequency divider MD is 112, the total frequency division ratio is (112) x (1176800) = (11153600
), and the frequency of the local synchronization signal SY is 2304×10
3 x (11153600) = 15Hz If the division ratio of the variable frequency divider ■ is 113, then (113) x (1176800
)=(11230400), and similarly the frequency of the local synchronization signal SY is 2304×103×(11230400
) = 10Hz, and the frequency of the phase signal P1 and TP2
It is possible to obtain a local synchronization signal SY that matches the ratio of .
Note that the variable frequency divider MD is normally set to 11, and is set to 112 only when the output of the drive circuit DR shown in Fig. 1 changes.
If the frequency is set to be divided, the configuration of the drive circuit DR can be simplified.

In FIG. 3, if the input signal A2 in FIG. 4 is applied to the input terminal, the pulse generator PG generates the pulse signal shown in FIG. 4b as described above, which is inverted by the inverter IVl. The pulse of c in the same figure is generated by the binary counter CT.
On the other hand, the first pulse of the first gate pulse generator GGl generates the first time gate pulse Dl, d2 in the figure.

The first gate pulse generator GGl has complementary outputs of 1 and 0, and 1 is normally the logical value "゜0゛, and 0 is the logical value "゜1゛. The logical values of both outputs are inverted. (Hereinafter, logical values will be written as "1゛" and "゜0゛.") Also, the second gate pulse generator GG2 is similar, but uses only 0 output, and the first gate pulse generator GGl It is excited by the 0 output and almost simultaneously generates a second time gate pulse corresponding to the second time gate shown in FIG. 4E2. First gate pulse generator GG to start input S of binary counter CTl
When the output of 1 is given, the counter CTl enters the operating state, counts the output pulses of the inverter I1, and calculates the output when the count content of h in Fig. 4 becomes the normal value by the second pulse. This state is maintained for a certain period of time, and the output from the inverter IVl is sent to the NAND gate G1, and as shown in FIG.
Only when the value becomes 1, the output of the NAND gate D1 becomes 6.
It will be 60″.

On the other hand, the output of the second gate pulse generator GG2 has its trailing edge delayed by the delay circuit DL, and is then inverted by the inverter 1V2, as shown in FIG. 4f, and is applied to the AND gate G3. The output during the period when E2 is "1" is taken out as shown in g in the figure in response to the end of the second time gate pulse E2.

That is, Tg is the delay time caused by the delay circuit DL. In addition, the outputs of NAND gate G1 and inverter IV2 are connected to A, which together with NAND gate G1 constitutes a reset circuit.
As shown in FIG. 4j, the ND gate G2 obtains an output that becomes ``1'' only during the period when both are ``1'', and the counter C
It is applied to the start input S of T2, and during the period of ゜“1゛, the counter C
Release the reset state of T2.

What should be noted here is the same figure? When the noise component N1 comes next to the phase signal S1 of
Since the output h is generated, the similar output B generated after this
3, the output 1 of the NAND gate G1 becomes "゜0゛", and the output j of the AND gate G2 also becomes "゜゜0゛. Therefore, at the time when it becomes "0'', the starting input S of the counter CT2 is not lost. Then, the counter CT2 is reset, which means that the output of the counter CTl in h of the same figure becomes ゜゜1.
This is performed every time the pulse generator PG produces an output during the period of ゛, and when the output of the inverter I2 shown in the figure f reaches ゜゜0゛, the counter CT2 stops operating. In this way, it is detected whether or not the pulse signal generated from the pulse generator PG during the first time gate period is a regular one, and from the fourth phase signal S4 onwards, it is determined that the pulse signal generated from the pulse generator PG is a regular one. Because it is the time width and period interval,
The output j of the AND gate G2 continues for the period of the gate pulse beat of ♂ in the same figure, which corresponds to the second gate time, and the counter CT2 performs a counting operation during this period. In fact, it is the gate pulse period Te plus the delay time Tg of the delay circuit DL, but this is used to take out the counting result when the counter CT2 completes counting, as described later. Therefore, it can be considered that the beat period counter CT2 essentially performs a counting operation. counter C
T2 is composed of three stages of binary counting circuits, and the third
As shown in the figure, there are three sets of complementary outputs of 1 and 0 #1 to #3, and in the reset state, output 0 is ゛゜1 - output 1 is ``゜0゛. When a pulse is applied, the output of #1 is inverted, and when the next pulse is input, the inverted state is restored, and this is repeated thereafter.

Further, when the output of output #1 of #2 returns, it is inverted, and when output #1 returns again, output #2 also returns. In addition, #3
Similarly, the output of the output #2 is reversed when the output #2 returns, and when the output #2 returns again, the output returns itself. These relationships are as shown in K2, I-, , m1 in FIG. FIG. 5 shows the operations after the counter CT2 corresponding to FIG.
It becomes the output state of rl2. These outputs are the AN in Figure 3.
D gate G5, and complementary outputs K2, L2, ml are given to AND gate G4, but in FIGS. 4 and 5, only AND gate G5 is directly involved in determining the reception speed, so output Kl , Ll, m2 will be described first.
In FIG. 5, regarding the pulses C1 to C6 of c based on the input signal containing noise components, the intervals between these pulses are irregular, so the counter CT2 does not count normally. A
Even when the output g of ND gate G3 becomes ゜“1゛,
The output k1 of counter CT2 is 0, so AND gate G5 produces no output.

On the other hand, after the pulse C7 in the normal state, the counter CT2 normally counts the pulses C7 to C9 during the second time gate period when the signal j in FIG.
Since the outputs Kl and Li are ゜゜1゛ and the output M2 is also ゛1゛, the pulse of g is given in response to the end of the second time gate pulse, so that all the inputs of the AND gate G5 become ``1''. The count output of counter CT2 is sent out via AND gate G5, and at output 0, "
R3, which sets flip-flop FF2. In addition to the trigger input T, the flip-flops FFl and FF2 have J and K inputs and complementary outputs of 1 and 0. By setting, the output 0 of the flip-flop FF2 changes from "1" to "0" as shown in Q2. Become.

On the other hand, the inputs of gate G4 of M are K2, L2, ml in FIG.
When a pulse of g is given as shown below, both “゜0
'', the output n of the AND gate G4 also remains ``0'', the flip-flop FFl is not set, its output 1 is ``0'' as shown in P1, and the output 0 is ``1''. Therefore, one of the inputs of the NAND gate G,
0, the output s becomes 1, and a positive bias is applied to the base of the transistor Q, making it ON, operating the relay RL, closing its contact RI, and activating the image receiving section.

On the other hand, the input of NAND gate G6 is P1 is ゜“0゛”, Q
Since 2 is ゜゜0゛, it is still ゜゜1 as shown in Figure 5 r.
゛ and does not change.

At this time, if the frequency division ratio of the variable frequency divider is set so that when r is ゜"r', it is 113s, when 6゜0゛ is 112, local synchronization can be achieved in accordance with the period of the low-speed phase signal TP2. The signal SY has a frequency of 10 Hz as described above.Flip-flop FFl is locked when the J input Q2 becomes "0" and maintains this state.

Next, the case where a high-speed phase signal is given as an input signal will be explained with reference to FIG.

Figure a1 has the same period TPl as Figure 2 a1,
This shows a state in which the signal is received normally without any noise components. In FIG. 6, the output b1 of the pulse generator PG1, the output C1 of the inverter 1, the output D1, (12, e2) of each gate pulse generator GG1, GG2, and the output F of the inverter IV2...the output G12 of the AND gate G3. Advance counter C
The relationship between the output h of Tl, etc. is the same as in FIGS. 4 and 5, but since the period of the phase signals S1 to S6 is short and the interval between them is narrow, the gate pulse Te of E2 corresponding to the second time gate period During the period, gate pulses Dl and d2 are generated twice by phase signals S1 and S3, and along with this, 2
The output h of the advance counter CTl also occurs twice. Further, the counter CT2 counts quickly in the normal state, and when the output g of the AND gate G3 becomes "1", the outputs K2, l-, , m1 of the counter CT2 all become "1". At this time, the output n of the N1 gate G4 becomes ゛゜1゛, and the flip-flop FFl is set.

On the other hand, since the outputs Kl, Ll, m2 of the counter CT2 are all "0", the output of the AND gate G5 remains "00", and the flip-flop FF2 is not set. Therefore, the output 1 of the flip-flop FFl changes from "0" to "1" as shown in P1 in FIG. , the output r of the NAND gate G6 becomes "゜0゛", and the frequency division ratio of the variable frequency divider MD is 1.
13 to 112, and the frequency of the local synchronization signal SY is set to 15Hz in correspondence with the high-speed phase signal.

Furthermore, the output P2 of the NAND gate G7 becomes "0",
Since Q2 remains at "1", the output s changes to "1" as in FIG. 5, operating relay RL.

In this way, the counter CT2 counts the number of pulses from the pulse generator PG during the output period of the second gate pulse generator GG2, and sets the frequency of the local synchronization signal SY according to the counting result. During the output period of the gate pulse generator GGl, it is detected whether the pulse signal from the pulse generator PG is a normal number or not, and when it is determined that the number is irregular, the operation of the counter CT2 is reset, so that the local synchronization signal SY
is not set and relay RL does not operate, so the image receiving unit does not start.

Note that flip-flop FF2 is locked by setting flip-flop FFl, as in the case of FIGS. 4 and 5, and the function to prevent malfunction when the input signal contains a noise component is also the same as described above. It is.

In addition, in the above explanation, the first time gate (revised p.
1-TO)≧Td>TP2, and the second time gate is (
4TP1-TO)≧Chi〉Here P2, but if the first time gate period is further extended to include two or more regular phase signals, and the second time gate period is extended accordingly, the phase signal From the start of reception to setting the local synchronization signal SY and starting the image receiving section. Even if the time required to reach the target increases slightly, the detection accuracy can be improved.

However, in conjunction with this, it is necessary to set the count of each counter CTl, CT2, and as the count of counter CT2 increases, the number of digits of its outputs #1 to #3 also increases, so the AND gate G4, It is necessary to increase the number of G5 inputs. Note that if the AND gates G4 and G5 are formed as an AND matrix, the combination of input conditions becomes arbitrary, and the number of pulses taken out as the counting result can be easily changed according to the usage conditions. In addition, for communication speeds of three or more, AND gates G4, G5, flip-flops FFl, FF2, NAND gates G6, G7, etc. are added according to the number of communication speeds, and the frequency of the variable frequency divider MD is divided. Similar results can be obtained if the ratio is prepared according to the communication speed.

In addition, there are infinite selections and combinations of the configuration of the logic circuit according to the type of circuit element, logic value polarity, etc. within the scope of the present invention, but it goes without saying that it can be arbitrarily selected according to the design conditions. As is clear from the above explanation, since the present invention is entirely composed of logic circuits, there is no need for expensive filters, the circuit operation is stable and reliable, and the device price is low. However, there is no risk of misidentification or malfunction due to noise components mixed into the line, and the communication speed is automatically set, so it can be used not only for various facsimile receivers but also for similar communication devices. can be obtained.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, in which Fig. 1 is a block diagram of a schematic configuration, Fig. 2 is a waveform diagram of a phase signal, Fig. 3 is a concrete block diagram, and Figs. 4 to 6 show each part. 3 is a time chart showing signal waveforms. IN...Input terminal, PG...Pulse generator (generates a pulse signal with a predetermined period), GGl...
・First gate pulse generator (first time gate setting),
GG2...Second gate pulse generator (second time gate setting), CTl...Binary counter, CT2...
...Counter, Gl, G6, G7...NAN
D gate, G2, G3, G4, G5...AND
Gate, FFl, FF2...Flip-flop,
XG...Oscillator, MD...Variable frequency divider, F
D: Fixed frequency divider, SY: Local synchronization signal.

Claims (1)

[Scope of Claims] 1. In a facsimile receiver that detects the cycle of a phase signal arriving from a facsimile transmitter and automatically switches communication speed, a pulse signal of a predetermined cycle is generated based on an input signal having a fixed time width or more. The pulse signal sets a first time gate having a time width that includes two or more regular phase signals, and a second time gate having a time width that includes more regular phase signals than the first time gate. , detecting whether or not the number of pulse signals of the predetermined period is normal during a first time gate period, and counting the number of pulse signals of the predetermined period during a second time gate period; Automatic speed switching of a facsimile receiver, characterized in that the frequency of a local synchronization signal that controls the operation of the facsimile receiver is set according to the result of counting the number of pulses during a second time gate period only when the result is normal. Method. 2. An oscillator with a constant oscillation frequency and a variable frequency divider that divides the output of the oscillator according to the cycle of the phase signal sent from the facsimile transmitter and sets the frequency of the local synchronization signal that controls the operation of the facsimile receiver. a pulse generator that detects that the pulse width of the phase signal is equal to or greater than a certain time width and generates a pulse signal of a predetermined period; a first gate pulse generator that generates a first time gate pulse with a time width including two or more signals; and a first gate pulse generator that is driven by the output of the first gate pulse generator to generate more regular phase signals than the first time gate pulse. a second gate pulse generator that generates a second time gate pulse having a time width including the first time gate pulse; a first counter that counts the pulse signal from the pulse generator only during the period of the first time gate pulse; and a first time gate pulse. a second counter that counts the pulse signal from the pulse generator after the reset is released during the period; and a pulse signal from the pulse generator that occurs after the count content of the first counter reaches a normal value. a reset circuit that forcibly resets the second counter; a gate circuit that sends out the count output of the second count in response to the end of the second time gate pulse; 1. An automatic speed switching device for a facsimile receiver, comprising: a control circuit for controlling a frequency division ratio of a frequency transmitter.