JPS6050101B2 - solid-state imaging device - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a solid-state imaging device that converts one-dimensional, two-dimensional, etc. optical information into electrical signals, and eliminates the occurrence of pluming, which is a major cause of image quality deterioration when photographing a shining subject. The purpose is to do.

Blooming is caused by excess charge generated in excess of the maximum amount of charge that can be accumulated in the photoelectric conversion element in the light receiving area, which spreads around the area exposed to strong light (or the light source), or spreads along the screen vertically around that area. There are things that appear as bands that extend in different directions. In particular, the latter is a MOS device that is representative of the XY-address method, and an image sensor (Char-priming) that has a hybrid configuration using a water transfer method that combines a light receiving section of the X-Y address method and a horizontal transfer section of the charge transfer method.
This phenomenon appears conspicuously in Devlce (abbreviated as CPD). First, we will explain the configuration and operation of the CPD, then show the conditions under which a blooming state occurs, and then describe conventional examples including countermeasures for removing the blooming state attempted in MOS devices.

As mentioned above, CPD uses the XY addressing method, especially the light receiving part and vertical scanning circuit of the MOS device, which is a typical example.
The charge transfer method, especially the horizontal CCD section of a typical CCD device, is combined with a vertical-to-horizontal conversion means consisting of a priming transfer section consisting of, for example, two transfer gates and one storage section, thereby creating a hybrid system. This device has a unique structure and is characterized by the fact that, in principle, fixed pattern noise does not occur.

The applicant has filed Japanese Patent Application No. 54-85274 (Japanese Unexamined Patent Publication No. 56-89)
We have already proposed a method for reducing blooming in such CPDs (see Publication No. 68).

The contents will be explained based on FIG.

In FIG. 1, all MOSFETs are of n-channel type. When an address pulse is applied to the row line 104 from the vertical scanning circuit 101, the MOSFETIO3 whose gate electrode is connected to the row line 104 is connected to the other MOSFETIO3 arranged in the same row.
It becomes "ON" together with OSFET. At this time, p-n
Signal charges photoelectrically converted by the junction photodiode 102 move to a column line (vertical signal line) 105. on the other hand,
By applying a positive voltage from the terminal 111 to the gate 112, the drain 110 of MOSFETIO6 is at a constant potential V.
It is set to D.

After that, by applying a positive voltage to the terminal 107, the MOSFET
IO6 is set to a potential V that is deeper than VD. When it is "ON", a bias charge corresponding to the difference (Vs-VD) between the potential VD of the drain 110 of MOSFETIO6 is applied to the MOSFET IO6.
Capacitor 10 connected to drain 110 of TlO6
9 to column line 105.

This bias charge is called a "priming charge", and the name derives from the fact that the operation of carrying a signal charge on top of this bias charge (i.e., priming charge) is similar to the action of priming, as will be described later.

According to the results so far, both the signal charge read from the photodiode 102 and the bias charge exist on the column line 105. The other column lines are similar. Next, terminal 1
When a positive voltage is applied to MOSFET 108, the drain 1 of MOSFET lO6 flows through the capacitor 109 due to the electrostatic induction effect.
Since it is superimposed on the potential of 10, it becomes ■M, which is deeper than ■s. Therefore, as a result of Vs × M, column line 105
The upper signal charges and bias charges are transferred to the drain 110 side of MOSFET lO6, which is potentially the deepest. This state is similar to the operation of priming water to obtain more water, so it is called ``priming water transfer.'' MOSFE
Of the signal charges and bias charges primed and transferred to the drain 110 of TlO6, only the signal charges are transferred to the transfer gate 112 (this is the drain 11 of MOSFET lO6).
0) to the horizontal CCD 13l.

This method of transferring only signal charges through the gate is called a skimming operation because it is similar to the operation of removing the supernatant liquid, and the transfer gate 112 that performs this operation is also called a skimming gate.

Next, the horizontal CCD 13l performs a horizontal transfer operation of the signal charge.

Note that the horizontal CCD 13l has a source electrode 113, a drain electrode 123, an input gate 114, and a floating diffusion gate 124, like a normal line CCD.
A floating diffusion amplifier (E.
D. A) 125, 4-phase drive electrodes 117 to 120,
It consists of an output gate 121, a reset gate 122, etc., and receives a signal output from a terminal 130 as a change in potential across a load resistor R. Specifically, for example, signal charges on the column line 105 are carried to a depletion layer formed under the drive electrodes 126 to 129 corresponding to one bit of the horizontal CCD 13l, and then horizontally transferred. Further, the drive pulses applied to the four-phase drive electrodes 117 to 120 of the horizontal CCD 13l are applied to the electrodes wired on the drive electrodes corresponding to each bit and provided with contacts as indicated by black marks. On the other hand, horizontal CCDl3l
When the charge carried from the column line is unnecessary or needs to be removed, a positive voltage is applied to the clearing terminal 115 to remove the unnecessary charge to the external power supply E.

For example, unnecessary charges on the column line 105 may be removed from the drive electrode 12.
When transferred to the depletion layer corresponding to one bit formed by 6 to 128, this unnecessary charge is transferred to the clearing terminal 115.
The clear gate 11 becomes “゜0N” by applying a positive voltage to
6 to the external power supply E. Therefore, when horizontally transferring signal charges, the pulse applied to the clear gate 116 is removed. In the above manner, only the signal charge without unnecessary charge is transferred to the horizontal CCD by CPD.
It is possible to horizontally transfer the signal using 3L and read it out as a video signal.

However, in a CPD with such a configuration, the excess charge generated in the photodiode in the blooming state overflows onto the column line through the channel of the gate part of the MOSFET, which has a slightly lower potential than the surrounding area.
The total amount of charge that can be removed across the horizontal CCD13l to the external power supply E is determined by the maximum amount of signal charge that can be transferred by priming transfer, and this amount is several times the maximum accumulated charge amount of the photodiode in the design. This is the limit.

In other words, this is the limit of blooming suppression degree. Therefore, it is desirable to introduce a new structure and configuration to efficiently eliminate any more excess charge. Up until now, as measures to remove the excess charge that occurs in such a blooming state, there have been two approaches: structural measures, in which special elements or configurations are used in the first photoelectric conversion section, and structural measures have been introduced in the second photoelectric conversion section. "゜Circuit countermeasures゛l" which is performed by circuit processing instead of
You could think so.

2, since a structurally complex configuration is removed from the circuit without introducing it into the light receiving section, it is possible to improve the performance regardless of the mass productivity of the image sensor.

However, with methods that theoretically eliminate the occurrence of blooming, the limit is to suppress the occurrence of blooming to about 150 degrees of the saturated signal charge, and uncertainties due to fluctuations in operating conditions depending on voltage, temperature, etc. cannot be avoided. . Therefore, this is not an essential countermeasure. In comparison, method 1 can theoretically prevent the generation of excessive voltage, and can be an essential countermeasure.

However, since the process is inevitably complicated, unless the effect of preventing blooming from occurring is significant, the burden on mass production will only increase. Although no structural countermeasure method with a significant blooming prevention effect has been proposed so far, attempts to reduce the blooming problem have been made using MOS devices.

In the following, after explaining the blooming state using FIGS. 2 and 3,
In the conventional example where the OS device has a specific configuration,
The structure, operation, drawbacks, etc. of the photoelectric conversion unit will be explained.

[Photodiode in blooming state] Figure 2a shows
The light receiving section of a MOS type solid-state imaging device is exactly the same as the light receiving section of a CPD.

) is shown as an equivalent circuit, focusing on the photodiode section of 201, and Figure 2b shows the MOSFET, 2O7C'0, corresponding to the photodiode 201 that is exposed to strong light.
FIG. 3 is a diagram showing potential (in the FF state). The photodiode 201, which is exposed to strong light, becomes forward biased by the large amount of charge 209 shown in FIG. 2b accumulated therein! Ru.

After that, the charge generated by photoelectric conversion is transferred to the gate 204.
, a source 205, and a drain 206.
spills onto column line 203 through parasitic transistor 208, shown in FIG. 2a, formed below 2O7. The charges 211 overflowing in one horizontal period are read out at the same time as the charges of other photodiodes connected to the same column line 203 are read out in subsequent horizontal periods, resulting in blooming.

Incidentally, in FIG. 2A (7), CpD indicates the equivalent capacitance of the photodiode, and CAL indicates the equivalent capacitance of the column line 2043. In order to suppress this blooming state, a vertical n+Pn structure attempted in a MOS device will be explained in principle with reference to FIG.

[Blooming countermeasures using vertical n+Pn structure] Figure 3a
indicates a photodiode section having an n+Pn vertical structure.

The area around the photodiode is separated from other photodiodes by a LOCOS oxide film 302. Light 301 incident on the n+ layer photodiode 305 is absorbed by Si to create electron-hole pairs, and electrons are accumulated in the n+ region 305, while holes are collected in the p-well 303 and connected to the negative side of the external power source E. It can be discharged to the side.

Note that the electrons generated in the n-substrate 304 are directly transferred to the n-substrate 30.
4 to the positive side of the external power source E, and the holes are collected in the p-well 303 and similarly discharged to the negative side of the external power source E. Therefore, the electrons accumulated in the photodiode 305 are generated in the n+ region 305 and the p well 303.

[Explanation of blooming suppression operation]

FIG. 3b shows an equivalent circuit of the photodiode section of FIG. 3a.

CpO is the junction capacitance of the photodiode 305, and Q is M consisting of the gate 306, source 305, and drain 308.
It is an OSFET, and TH is a lateral Np parasitic to Qv.
n bipolar transistor, photodiode 3
05 as emitter (E), p-well 303 as base (B)
, the drain 308 connected to the column line 307 is used as a collector (C).

On the other hand, Tv is a vertical transistor obtained by a vertical Npn structure, and the n-type substrate 304 is a transistor Tv
It has become a collector of. As shown in Figure 3c, if the collector areas of both transistors TH and Tv are A8 and Av, and the current amplification factors are expressed as H, e (H), Hfe, V), the ratio of their currents RVH is as follows. become that way. However, here, WV, . WH is the base width of the transistor Tv, TH, L
Electron diffusion distance in NP well region, LN>Wv, LN>
Since WH can be set, equation (1) can be simplified as follows.

〔effect〕

In general, the collector area Av is equal to the area of the photodiode 305, and on the other hand, the effective area AH is also (Av/AH) because it is necessary to consider the influence of the adjacent surface.
is approximately 10 to 20 times larger.

Furthermore, due to constraints such as actual layout area (WH/W
The reality is that it has to be about 1. As a result, even if the blooming occurs in a vertical n+Pn structure, it is expected that the improvement will be limited to about 10 to 20 times, and actual experimental results show similar values. [Disadvantages] Moreover, as image sensors become smaller, (Av/AH)
As the value of becomes smaller and smaller, it becomes clear that the blooming countermeasure using the vertical n+Pn structure is by no means a fundamental countermeasure.

At this time, for example, due to advances in process technology, PVH】10~
Even if the value of 20 is maintained, the blooming suppression effect will not be sufficient to compensate for the complexity of the process.

Therefore, there is a need for an effective method, since similar effects have been obtained experimentally using simple circuit processing as shown in Japanese Patent Laid-Open No. 54-96321. If blooming countermeasures are taken using structural countermeasures that complicate the process as described above, the suppression effect must be at least one to two orders of magnitude greater than the suppression effect achieved by circuit countermeasures. The present invention introduces a new vertical structure to the photodiode section of an image sensor. By incorporating this structure into the light receiving section of a CPD, for example, the ability to remove blooming can be dramatically increased, and in principle, blooming does not occur. There are things that make it possible to realize functions that are not possible.

The new vertical structure introduced in the photodiode section is a vertical n+n-n+ structure, with p
The bias applied to the region controls the depletion layer in the region.

Before going into the description of specific embodiments, we will explain the basic principle of a static induction transistor (Static Induct transistor) to explain the operation of a vertical n+n-n+ structure with a p+ gate section.
iOntransjstOr abbreviated as S. I. It's called T.

) operation is explained. [S. I. Structure and operation explanation of T] Figure 4a shows the basic structure of SIT.

In an SIT (currently, the junction type is targeted. The symbol representation of the SIT is shown in FIG. 4b), which is composed of the same conductivity type (here, n-type) from the source 401 to the drain 403. An operation is performed in which the amount of majority carriers flowing toward the drain 403 is controlled by the potential of the gate 405. Moreover, channel 409
It has a characteristic that the impurity density (NO) of
−n+ structure. Impurity density of channel 409 (NO
) is low, so in SIT, the channel is already in a pinch-off state completely covered by the depletion layer 410 at zero gate bias or when a slight reverse voltage is applied to the gate. According to FIG. 3c, which shows the potential of the -B'' cross section, a potential barrier 407 (in the shape of a saddle point) appears in front of the source, and the height of this potential barrier mainly controls the flow rate of carriers flowing from the source 401 to the drain 403. Do the following.

This potential barrier 407 is a true gate (intrinsic gate).
(gate).

The drain current is determined by carriers flowing across this barrier from the source 401 (having a source potential 404) to the drain 403 (having a drain potential 406). Furthermore, even with a small drain voltage, the entire region between the gate 402 (which has a gate potential 405) and the drain 403 becomes a depletion layer, and when a higher drain voltage is applied, the drain potential 406 decreases, almost in proportion to the lower drain voltage. true gate 407
The barrier height decreases, and at the same time, the barrier position moves toward the source 403, so the amount of carriers crossing the barrier 407 increases, and the drain current increases as the drain voltage increases.

Carriers that have crossed the potential barrier 407 travel at almost saturation speed due to the drift electric field in the n-region 409.
The drain current is almost proportional to the amount of carriers that cross the potential barrier 407. The output characteristic of the resultant βIT shows an unsaturated characteristic. On the other hand, other features of SIT whose operation mechanism is majority carrier injection amount control are that the temperature characteristics are negative in the large current region, the resistance of the channel 409 is small, so the thermal noise is extremely small, and the It has low noise characteristics, with shot noise being the main noise source.

In addition, in FIG. 4d, the channel impurity concentration ND (Cm-3
) and the channel thickness d(μTrL, ), SIT
A range 408 (shaded area) in which the operation can be realized is shown.

However, it is known that even a large impurity concentration NO is sufficient when the individual components are integrated into an IC. Furthermore, by controlling the channel dimensions and impurity concentration, junction SITs can be designed into either a normally-on type, which is conductive at zero gate bias, or a normally-off type, which is turned off at zero gate bias. It has the following characteristics. Normally off type SIT
BSIT is also called BSIT, and like bipolar transistors, a forward bias of more than a certain value is applied to the gate.
It shall be N. A method for counteracting blooming by introducing a vertical n+n-n+ structure having a p+ gate section, which is found in this SIT, into a photodiode section will be described below based on an embodiment.

[First Embodiment of the Present Invention] FIG. 5a shows a structure in which a vertical n+'n+ structure is introduced into a photodiode section separated by a LOCOS oxide film 501.
The p-well 502 surrounding the n-region 505 is the n-region 5.
It serves as a gate for the 05 channel.

In other words, the applied voltage E between the p-well 502 and the substrate 503
'' to determine the conduction state by controlling the potential barrier set by the depletion layer 506 generated in the channel which is the n-region 505. In a light input state that does not cause blooming, the source-resistant region 504 is closed by photoelectric conversion. The accumulated electrons are read out to the drain region 508 by applying a voltage to the gate electrode 507, taken out to an aluminum wiring 509, etc., and then read out to the outside.

On the other hand, when strong light that causes blaming occurs in a normal device, excessive charges exceeding the maximum accumulated charge amount of the n+ source region 504 are transferred to the n+ substrate 503 at a vertical velocity.
It is possible to remove the external power source E'' through the external power source E''.

This can be realized by setting the barrier potential of the channel in the region to a potential V2 slightly lower than the barrier potential V of the channel below the gate 507. This photodiode equivalent circuit is expressed as a combination of a photodiode 510 and an SIT 5ll, as shown in FIG. 5b. Note that CPD in FIG. 5b indicates photodiode equivalent capacitance, and CA indicates column line capacitance. FIG. 5c is a potential diagram of the A-A'' cross section and the B-B cross section of the photodiode shown in FIG. 5
If a voltage is applied to the p-well 502 so as to have a barrier potential V2 of 05, the excess charge 512 will be discharged to the external power source E'' through the substrate 503 side.

An image sensor using such a photodiode section as a light receiving section will be explained with reference to FIG. All MOSFETs are n-channel. When an address pulse is applied to the row line 605 from the vertical scanning circuit 601, the MOSFET 6O3 whose gate electrode is connected to the row line 605 becomes 6° C.NO together with the other MOSFETs lined up in the same row.

At this time, the signal charge photoelectrically converted by the pn junction photodiode 602 moves to the column line 606. At this time, if strong light is irradiated onto the photodiode 602,
The excess charge generated by photoelectric conversion is '6' of MOSFET6O3.
It is discharged to the external power source E'' through SIT6O4, which has a channel barrier potential slightly lower than the channel barrier potential at 0FF''. This also applies to other photodiodes. After that, the signal charges read out on all the column lines including the column line 606 are output to the output terminal 1 as a video signal.
The configuration to obtain from 30 is the part specified by M,
This is exactly the same as the part designated by M in FIG. 1, and the operation method is the same as in FIG. As shown in this example, by introducing a vertical n+n-n+ structure with a p+ gate section into the photodiode section, even if excessive charge is generated due to strong light being irradiated onto the photodiode, the external power source E'' can be used. Excess charges are discharged to the external power source E through the SIT structure with a set barrier potential, so that blooming does not occur in principle.

Next, instead of discharging the unnecessary charges or leftover charges on the column lines (606, etc.) across the priming transfer stage and the horizontal CCD 13l to the external power supply E, they are directly connected vertically to the n+ An image pickup device constructed of a light receiving section in which both the photodiode and the drain have a vertical n+Pn+ structure in order to extract the light to the external power source E'' through the substrate will be described with reference to FIGS. 7 and 8.

[Second Embodiment of the Invention] FIG. 7a shows an n+
An n-type resistive structure is introduced, and the p-well 702 surrounding the n-type region 705 serves as a gate for the channel of the n-type region 705.

In other words, a depletion layer 7 is formed in the channel of the n-region 705 due to the applied voltage E'' between the p-well 702 and the n+ substrate 703.
The conduction state is determined by controlling the potential barrier set by 06. In the case of optical input that does not cause blooming, electrons accumulated in the n+ source region 704 due to photoelectric conversion are read out to the n+ drain region 708 by applying a voltage to the gate electrode 707.

At this time, since the aluminum wiring 709 is in a capacitive couple state with DC insulation from the n+ drain region 708, a potential change corresponding to the potential change of the n+ drain region 708 is generated by electrostatic induction, and this is sent as a signal to the output section. Can be read. Note that after detecting the signal charge read to the n+ drain region as a potential fluctuation of the aluminum line 709, a pulse is applied to the aluminum line 709 from the terminal 711 via the capacitor 710. This is further connected to n+ via capacitor 715.
applied to drain 708. This utilizes the bootstrap effect to lower the potential of the drain region 708 to a deep V
3 (FIG. 7c) to a shallow V''3. As a result, the potential V''3 of the drain 708 is lower than that of the n-region 7 below the drain.
12 (FIG. 7c). As a result, unnecessary electrical stations remaining in the n+ drain region 708 after detection are passed through the n+ region 712.
On the other hand, when strong light that would cause blooming in a normal element is incident, the n+ source region 704
Excess charge exceeding the maximum accumulated charge amount is vertically transferred to the n+ substrate 7.
03 to an external power source E''.

This can be realized by setting the barrier potential of the channel in the n-region to a potential (4) that is slightly lower than the barrier potential V5 of the channel below the gate 707. The equivalent circuit of this photoreceptor is shown in FIG.
It is expressed as a combination of 7l4. Note that, in FIG. 7b (7), CpD is the photodiode equivalent capacitance, and CD is the drain equivalent capacitance. Figure 7c is the fourth
These are potential diagrams of the C-C'' cross section and the D-D'' cross section of the light-receiving part in Figure a, where a potential lower by Δ■ than the potential V5 set by the gate 703 is the barrier potential ■4 of the channel 705 in the n-region. .

This can be set by the voltage relationship between the p-well 702 and the n+ substrate 703, and as a result, the excess charge 715 is removed from the substrate 703.
It will be discharged to the external power source E'' through the 03 side.
An image sensor using such a light receiving section will be explained using FIG. 8.

All MOSFETs are n-channel. Vertical scanning circuit 8
When an address pulse from 01 is applied to the row line 809, the MOS whose gate electrode is connected to the row line 809'
FET8O5 becomes '40N'' along with other MOSFETs lined up in the same row. At this time, the signal charge photoelectrically converted by photodiode 802 moves to drain part 806. As a result, electrostatic induction via capacitor 807 , a potential change that has a certain relationship with the signal charge is generated on the column line 808. The fact that this potential change occurs on the column line 808 equivalently corresponds to the movement of the signal charge onto the column line 808. do.

At this time, if there is strong light incident that would cause blooming in a normal device, the excess electricity generated by photoelectric conversion will be transferred to the MOS.
It is rejected to the external power supply E'' through SIT8O3, which has a channel barrier potential set slightly lower than the channel barrier potential of FET8O5.Therefore, blooming does not occur in the photodiode 802 in principle. By applying a positive voltage to MOSFET 818, the drain 816 of MOSFET 815 is set to a constant potential VD.

After that, a positive voltage is applied to the terminal 812 and the MOSFET 8
When l5 is set to ゜゜0N゛ at a potential ■3 deeper than VO, the potential ■ of the drain 816 of MOSFET 8l5. The bias charge corresponding to the difference (■, -■.) from the MOSFE
Capacitor 81 connected to drain 816 of T8l5
7 to column line 808. This injected charge is “
It is a priming charge and an internal bias charge. In the operation so far, the photodiode 8 is on the column line 808.
There are both equivalent signal charges and bias charges that have a fixed relationship with the signal charges read from 02.

Next, when a positive voltage is applied to the terminal 813, it is superimposed on the potential of the drain 816 of the capacitor 817 due to the electrostatic induction effect, so that the voltage becomes a potential (9) deeper than V.

Therefore, the signal charge and bias charge on the column line 808 are transferred to the drain 81 of MOSFET 8l5, which has the deepest potential (9).
Transferred to the 6th side. This state is called priming transfer. On the other hand, after the signal charges on the column line 808 move to the capacitor 817, the signal charges transferred from the photodiode 802 to the drain part 806 of MOSFET8O5 are no longer needed, so a pulse is sent from the terminal 810 to the aluminum line 808 via the capacitor 811. Apply. It is further applied to drain 806 via capacitor 807. This uses the electrostatic induction effect to change the potential of the drain 806 to the external power supply E''
This means that the potential is raised to a level smaller than the barrier potential of the channel of SIT8O4 set by . As a result, M.O.
The unnecessary signal charge remaining in the drain 806 of SFET8O5 is discharged to the external power supply E'' through SIT8O4.Next, as described above, from the column line 808, M
Among the signal charges and bias charges primed and transferred to the drain 816 of the OSFET 815, only the signal charges are transferred through the transfer gate 816. The signal is transferred to the horizontal CCD 819 by the skimming operation. After this, horizontal CCD
8l9 performs a horizontal transfer operation for signal charges.

Note that the horizontal CCD 8l9 has a source electrode 820, a dot 820, and Rain electrode 832, input gate 821, floating diffusion gate 83
Floating diffusion amplifier (E
．． D. A) 834, four-phase drive electrodes 822 to 825, an output gate 830, a reset gate 831, etc., and a signal output is obtained from a terminal 835 as a change in the potential of the load resistor RL. Specifically, the signal charge on the column line 808 is carried to a depletion layer formed under the drive electrodes 826 to 829 corresponding to one bit of the horizontal CCD 819, and then horizontally transferred. Furthermore, the drive pulses applied to the four-phase drive electrodes 822 to 825 of the horizontal CCD 8l9 are wired on the drive electrodes corresponding to each bit, and the black marks ? is applied to the electrode providing the contact. As described above, according to the second embodiment of the present invention, the photodiode formed in the p well serving as the p+ gate part and the vertical n+
Due to the n-n+ structure, the excess charge photoelectrically converted by the photodiode in response to strong light incidence is carried vertically to the substrate and discharged to the outside, so that blooming does not occur in principle.

2. After the potential change on the column line corresponding to the signal charge moved from the photodiode to the drain part is read out, the unnecessary signal charge remaining in the drain part is removed by reducing the potential of the drain part. The drain portion can be reliably reset because the drain exceeds the barrier potential of the n-region corresponding to the channel of the SIT structure under the drain and discharges to the n+ substrate.

It is possible to realize this advantage. Next, if a vertical n+n-n+ structure is introduced to the charge injection device (ChargeInCtiOnDevice), the time required to inject unnecessary charges into the substrate can be extremely shortened.
This enables miniaturization and high pixel density, which was previously considered difficult to achieve.

Regarding this, as a third embodiment of the present invention, FIG.
This will be explained next based on Figure 0. [Third Embodiment of the Present Invention] FIG. 9a shows a structure in which a vertical n+n single resistance structure is introduced under gates 903 and 904 that control the n+ region 902 of the light receiving section separated by a 10C0S oxide film 901. The p-well 907 surrounding the n-regions 905 and 906 serves as a gate for controlling the channel depletion layers 908 and 909 of the regions.

Note that the p+ region 910 is for electrically isolating the gates 903 and 904 so that their effects work independently. Depletion layers 908, 90 in n-regions 905, 906
9 is controlled by an external power supply F applied between the p-well 907 and the n+ substrate 911, and as a result, the n-regions 905, 9
The barrier potential of channel 06 is set.

This makes it possible to determine the conduction state of the SIT consisting of the vertical n+n-gi structure and the surrounding p-well. In the case of light input that does not cause blooming in a normal image sensor, when a voltage is applied to both gates 903 and 904, photoelectrically converted charges are accumulated in n+ region 902.

The method of reading out this charge is as shown in FIG.
For the state where voltage is applied to both 03 and 904, gate 9
When the applied voltage 04 is removed, the photoelectrically converted charges 912 are all transferred to the depletion layer 918 under the gate 903 as shown in FIG. 9e.
are collected in. Thereafter, by setting the voltage of the gate 904 to the reference potential and removing the voltage applied to the gate 903, all the photoelectrically converted charges are collected in the depletion layer 919 under the gate 904, as shown in FIG. As a result, a signal is detected as a potential change of the gate 904 caused by electrostatic induction. Thereafter, the photoelectrically converted charges 912 are no longer needed, so by removing the voltage applied to the gate 904, the depletion layer potential V7 is vertically n+n-n+ as shown in FIG. 9g.
Since it is smaller than the barrier potential V6 of the channel in the region, n
Move to the sake board 911 through one area 905, 906,
On the other hand, when there is strong light incident that causes blooming in a normal element, the n+ region 9
It is necessary to move the excess charge 917 exceeding the maximum accumulated charge amount of 02 vertically to the n+ substrate and discharge it to the external power supply.

This can be achieved by setting the barrier potential of the channels of the n-regions 905 and 906 to a potential 6 that is slightly lower than the potential V7 of the buried channel of the bottom region 902 when the voltage applied to the gates 903 and 904 is removed. . The equivalent circuit of this light receiving section is as shown in FIG. 9b, with capacitors 913 and 91
It can be expressed by combining 4 and SIT9l5, 9l6.

Note that CV and CH in FIG. 9b are gates 903 and 90, respectively.
This corresponds to the capacitance of the depletion layer below 4. In addition, Fig. 9c
is a potential diagram of a cross section from E to E'' of the light receiving section in FIG.
Set the failure potential of the channel at 5,906 and the excess charge at 9
17 flows over this barrier to the n+ substrate side 911 and is discharged to the external power supply E''.

In addition, FIGS. 9 d to 9 g show a series of changes in the operating state from a state in which charges are accumulated after photoelectric conversion by light irradiation to the next accumulation state when a signal is read out.
9d corresponds to a non-selected state, FIG. 9e corresponds to a half-selected state, FIG. 9f corresponds to a read state, and FIG. 9g corresponds to a reset state.

Note that it is clear that the n-areas 905 and 906 may be made into one area in common. An image sensor using such a light receiving section will be explained using FIG. 10.

All MOSFETs are n-channel. Vertical scanning circuit 1
When no address pulse is output from 001, it is assumed that a positive voltage is applied to all row lines, similar to row line 1002.

As a result, photoelectrically converted signal charges are accumulated in a depletion layer formed under the gate connected to the row line. Now, when a negative direction pulse is applied to the terminal 810, the potential of the column line 1003 is raised via the capacitor 811 due to the bootstrap effect, which again raises the source potential of SITlOO7 via the capacitor 1005 due to the bootstrap effect. .

The unnecessary electric charge that has been applied to the source of the urine condensation βITlOO7 is removed to the external power supply E'' through the substrate, and then the terminal 8
When the 10 negative direction pulses are removed, the column line 1003 is at the potential set by the voltages applied to the terminals 812-814.
At this time, the signal photoelectrically converted in the light receiving section is transferred to the input (
For example, a potential greater than the potential of the column line is set for the row line so that the potential is accumulated in the depletion layer below the gate connected to the gate (eg, 1004).

Next, when a negative direction address pulse (hereinafter abbreviated as negative pulse) is applied to the row line 1002 from the vertical scanning circuit 1001, the gate 1004 connected to the row line 1009 The depletion layer under the gate disappears together with the gate. Therefore, the charge accumulated in the depletion layer under the gate connected to the row line 1003 to which the negative pulse was applied moves to the depletion layer under the gate connected to each column line (eg, 1003, etc.).

As a result, the potential on each column line changes due to electrostatic induction as a result of photoelectrically converted signal charges being collected under the gate connected to the column line. In this way, the potential change corresponding to the signal charge on the column line is read out to the output section 835 as a signal change by the operation of the N frame part in FIG. 10, which is configured similarly to the N frame part in FIG.

On the other hand, excess charge generated when strong light is irradiated to the light receiving part is removed from the SIT (for example, 1006, etc.) formed under the gate connected to the row line (for example, 1002, etc.) and the column line (for example, 1003). It passes through the SIT (for example, 1007) formed under the gate, passes through the substrate, and is discharged to an external power source E''.

As described above, according to the third embodiment of the present invention, 1. Due to the vertical n+n-n+ structure under each gate and the p-well gate configuration, excess charge generated in the light receiving section is carried to the n+ substrate via the n+n-n+ structure. Because it is discharged to the outside,
Blooming does not occur in principle.

Since the time required to inject two unnecessary charges into the substrate is fast, the time constant required for injection, which was a problem in conventional CID, is extremely short due to the contribution of the drift electric field due to the n+' resistance structure, making it ideal for high density.

It is possible to realize this advantage. In addition, the above 3
In one embodiment, the p-well portion having the gate function is grounded, but it may be operated by applying a negative voltage. Further, as shown in FIG. 11a, a p-well portion 11 serving as a gate for the channel of the n-region of the vertical n+n-resistance structure is provided.
01 does not need to be in contact with the substrate 1102, and may be separated from the n+ substrate 1104 as in the p well 1103 shown in FIG. 11b, as long as the depletion layer 1103 is sufficiently formed. As can be seen from the three embodiments shown above, according to the present invention, a vertical n+n-n+ structure having a p-well as a gate can be used as a BBD. The present invention can be applied to all types of light receiving sections of conventionally proposed image pickup devices such as CCDs, and as a result, it is possible to have the advantage that blooming does not occur in principle.

This has great value in dramatically expanding the performance of solid-state color cameras.

[Brief explanation of drawings]

Figure 1 shows the conventional Char? −
Basic circuit diagram of Priming-Device, Part 2
Figure 3a is an equivalent circuit diagram of the photodiode section in the blooming state, Figure 3b is a potential diagram of the MOSFET section in the state of Figure 3a, Figure 3a is a structural diagram of a conventional photodiode with blooming countermeasures, and Figure 3b is its equivalent circuit. Figure, same c.
4A is a structural perspective view of the same diode, FIG. -B'' line potential state diagram, d is a diagram showing the realization range of SIT operation, FIG. 5a is a structural diagram of the light receiving section of the first embodiment of the present invention,
The same b is the equivalent circuit diagram of a, and the same c is the same AOA-A'', B-B
6 is a circuit diagram of a solid-state image sensing device using FIG. 5, FIG. Equivalent circuit diagram, c is a potential state diagram of the (7) C-C゛, D-D'' line section, Fig. 8 is a circuit diagram of a solid-state imaging device using Fig. 7, Fig. 9
Figure a is a structural diagram of the light receiving section of the third embodiment of the present invention, figure b is an equivalent circuit diagram of a, figure c is a potential state diagram of the overlined part of a(7)E, and figure d-g are its operating states. 10 is a circuit configuration diagram of a solid-state imaging device using FIG. 9, FIG. 11A,
502, 702, 907... p-well, 504,
704,902...Chochu area, 503,703,
911... Substrate resistant, 505, 705, 905.
...n area.

Claims (1)

[Claims] 1 A high impurity concentration photoelectric conversion region of a second conductivity type selectively formed on one surface side of the semiconductor substrate of the first conductivity type, and a second conductivity type formed on the other surface side of the substrate. a low impurity impurity of a second conductivity type selectively formed in the substrate in contact with the photoelectric conversion region and the excess charge collection region and between these two regions; A solid-state imaging device characterized by having a vertical transfer region for excessive signal charge concentration.