JPS605006B2 - Key input method for computer with CRT display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key input method for an electronic computer with a CRT display device.

Conventionally, electronic computer systems have always incorporated a keyboard device as an input device and a CRT display device as an output device, but each of these two input/output devices is provided with an independent control section.

However, whether it is a keyboard device or a CRT display device, data in the refresh memory is dynamically read in the same way, and having a separate control section is advantageous from a cost standpoint as well as an input/output control system using software. It was also unreasonable from the point of view of simplification. This invention was made in view of the above points, and its purpose is to
An object of the present invention is to provide a key input method for an electronic computer with a CRT display device, which is improved in terms of cost and software by integrating the display device and the keyboard device into one control section.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, DB is a bidirectional data path connected to a CPU (central processing unit) (not shown), and is connected to the display refresh memory 11, and also receives key input commands KI from the CPU. Buffer 1 operated by
Connected to 2. In addition, the address data sent from the CPU via the address path AB and the CRT
CRT address signal C output from controller 14
RT/ADD is input to multiplexer 13. This multiplexer 13 selects address data from the CPU or address data from the CRT controller 14 in accordance with a select signal from the CPU, and sends it to the display refresh memory 11. This display refresh memory 11 receives read/write signals R/W from the CPU.
Reading or writing is specified by , and the output data is converted into serial data via a P-S (parallel-serial) conversion circuit 15 and sent to a CRT display device 16 as a video signal. The CRT display device 16 also receives horizontal synchronizing signals output from the CRT controller 14. SYNC and vertical synchronization signal V. SYNC is input. The CRT controller 14 outputs a CRT address signal to the multiplexer 13, and also inputs, for example, lower six bits of data to the decoder 17, data selector 18, and buffer 2, respectively.
Further, the output signal from the decoder 7 is input to the key matrix circuit 19. A signal output from the key matrix circuit 19 in response to a key operation is sent to the data selector 18 as a selection signal. Data selector 18 selects address data from CRT controller 4 in accordance with a select signal from key matrix circuit 19, and outputs one pulse signal to buffer 2 at the selection timing. According to the pulse signal from the data selector 18, the CRT controller 1
A part of the address data output from 4 is read into buffer 2. The data stored in the buffer 2 is read out in response to a key input read command KI from the CPU and transferred to the CPU via the data bus DB.
Next, the decoder 7, key matrix circuit 19, and data selector 18 will be explained with reference to FIG.
In this embodiment, the CRT controller 4 outputs 8-bit address data ~A7, and the multiplexer 1
3 to the display refresh memory 11, of which the lower 6 bits of data Ao to A5 are used as timing signals for key input. In other words, the 3 bits of A2 go to decoder 7, A3 to A5
3 bits are input to the data selector 18, and
Six bits Ao to A5 are input to buffer 2. The decoder 7 decodes the input 3-bit data A2 to obtain sequential pulses KIO to K17, and the timing signals KIO to K17 are input to the key matrix circuit 19. The key matrix circuit 19 is equipped with eight output lines KCO to KC7, and any one of the output lines KCO to KC7 is selected by a key operation, and an input timing signal KIO to KC7 is applied to the selected output line according to the operation key. K17 is output. On the other hand, the data selector 18 is configured to select input data based on the signals output from the output lines KCO to KC7 of the key matrix circuit 19, and output one pulse signal when the input data is selected. The output pulse signal is sent to buffer 2 as an input signal. Next, the operation of this invention will be explained.

Refresh memory 11 for displaying display data from the CPU
When writing, a write signal W is input from the CPU to the display refresh memory 11, and a select signal for selecting address path AB is input to the multiplexer 13. As a result, address data sent from the CPU via the address bus AB is input to the display refresh memory 11 via the multiplexer 13. Display data from the CPU is written to the specified address. Next, when outputting the display data stored in the display refresh memory 11 to the CRT display device, the read signal R is input from the CPU to the display refresh memory 11, and the CRT address signal CRT. Refresh memory 11 for displaying ADD
The select signal is input to the multiplexer 13
Enter. This allows CRT control. - The storage contents of the display refresh memory 11 are sequentially read out in accordance with the CRT address signal CRT/ADD output from the CRT controller 14, and are converted into serial data through a p-s (parallel-serial) conversion circuit 15. It is sent to the display device 16 and displayed. Next, we will explain what happens when a certain key is pressed.

Of the address data Ao to A7 output from the CRT controller 14, 3-bit data Ao to N is converted into timing pulses KIO to K17 via the decoder 17 and input to the key matrix circuit 19. Therefore, if a certain key is operated now, one of the output lines KCO to KC7 for that operated key is selected, and a timing signal KIO to KIO is sent to that output line.
One of 17 is output. For example, in Figure 2, "8
” is operated, the timing signal K
16 is output to the output line KC6, and the data selector 1
Sent to 8. The data selector 18 selects 3-bit data A2 to A5 from the RT controller 4 according to a signal from the key matrix circuit 19, and outputs one pulse signal at the selected timing. For example, if the timing signal K16 for the numeric key "8" is input from the key matrix circuit 19 to the data selector 18 via the output line KC6 as described above, the CRT controller 14 outputs &, A4, A.
When the 3 bits of 3 become "110", a "1" signal is output from the data selector 18. On the other hand, the timing signal A is output from the CRT controller 14.
The decoder 7 outputs when the 3 bits to 2, A, , are "001". Therefore, when the numeric key "8" is operated as described above, A5 to A are output from the CRT controller 4. When the 6 bits of the data become "110001", the data selector 18 outputs a "1" signal, which is sent to the buffer 2 as a read signal. Therefore, data "110001" of A5 to Ao outputted from the CRT controller 14 at this time is read into the buffer 12. The data held in this buffer 12 is
The data is read from the buffer 2 in response to a key input command KI from the CPU and transferred to the CPU via the data bus DB. Also, when other keys are operated, the data selector 18 outputs an input pulse to the buffer 12 at the timing specified for each key, and part of the address data output from the CRT controller 14 at that time is input to the key. C via buffer 12 as code
Sent to PU. As explained above, according to the present invention, the key input timing signal is generated using the CRT controller that specifies the address of the display refresh memory of the CRT, thereby simplifying the configuration of the key input control section. Therefore, it is possible to provide a key input method for a computer equipped with a CRT display device, which is improved in terms of cost and software.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention, and FIG. 2 is a configuration diagram showing details of the decoder, key matrix circuit, and data selector portions in FIG. 1. 11...Refresh memory for display, 12...
...Batsuhua, 13...Multiplexer, 14...
CRT controller, 15...P-S converter,
16...CRT display device, 17...decoder, 18...data selector, 19...key matrix circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. A CRT display device, a CRT controller that continuously specifies the address of a refresh memory that stores display data to be displayed on this CRT display device, and
a decoder that decodes an addressing signal output from the controller to generate a sequential pulse; a key matrix circuit that has a plurality of key switches and uses the sequential pulse output from the decoder as a timing signal for key sampling; and means for creating a key code based on a key operation signal from the CRT controller and an address designation signal from the CRT controller.
Key input method for computer with RT display device.