JPS6049650A - Formation of multilayer interconnection structure - Google Patents
Formation of multilayer interconnection structureInfo
- Publication number
- JPS6049650A JPS6049650A JP15847583A JP15847583A JPS6049650A JP S6049650 A JPS6049650 A JP S6049650A JP 15847583 A JP15847583 A JP 15847583A JP 15847583 A JP15847583 A JP 15847583A JP S6049650 A JPS6049650 A JP S6049650A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- film
- thin film
- layer
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、多層配線構造の形成方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for forming a multilayer wiring structure.
従来技術と問題点
従来、多層配線構造を形成するには、第１層配線層上に
眉間絶縁層を形成し、第１Ｎ配線層の厚みの分だけ盛り
上がった眉間絶縁層」二の段差が無くなるまで眉間絶縁
層を平坦化した後、更に眉間（１）
絶縁層の厚みを盛り上げ、この上に第２層配線層を形成
していた。しかしながら、眉間絶縁層が酸化シリコンや
窒化シリコン等の無色透明な物質であるため、これが平
坦化されたかどうかを筒中に検査することができず、平
坦化の失敗によって第２層配線層の断線等が生じていた
。Conventional technology and problems Conventionally, in order to form a multilayer wiring structure, a glabellar insulating layer is formed on the first wiring layer, and the glabellar insulating layer is raised by the thickness of the 1N wiring layer to eliminate the difference in level between the eyebrows. After flattening the glabellar insulating layer up to the glabellar insulating layer, the thickness of the glabellar insulating layer (1) was further increased, and a second wiring layer was formed thereon. However, since the glabellar insulating layer is made of a colorless and transparent material such as silicon oxide or silicon nitride, it is not possible to inspect the inside of the cylinder to see if it has been flattened, and failure in flattening may cause disconnections in the second wiring layer. was occurring.
発明の目的
本発明は」−記従来の問題点に泥みてなされたものであ
り、その目的は、平坦化の度合を簡１１に検査して断線
等を有効に防１１二することができる多層配線構造の形
成方法を提供することにある。OBJECTS OF THE INVENTION The present invention has been made in consideration of the problems of the prior art, and its purpose is to provide a multi-layer structure that can easily inspect the degree of flattening and effectively prevent wire breakage. An object of the present invention is to provide a method for forming a wiring structure.
発明の構成
上記目的を達成する本発明は、平坦化後の層間絶縁層」
二に有色不透明薄膜を形成し、該有色不透明薄膜」二の
段差を光学顕ｉ；’＆鏡で検査することにより、前記層
間絶縁層の平坦化の度合を検査する工程を含むように構
成されている。Structure of the Invention The present invention achieves the above objects by forming an interlayer insulating layer after planarization.
forming a colored opaque thin film on the second layer, and inspecting the degree of planarization of the interlayer insulating layer by inspecting the level difference in the colored opaque thin film with an optical microscope and mirror; ing.
以下２本発明の更にｉ′を細を実施例により説明する。Hereinafter, the details of i' of the present invention will be explained with reference to two examples.
発明の実施例
（２）
図のＡ乃至、Ｉは２本発明の一実施例の形成工程を示す
素子の要部断面図である。Embodiment (2) of the Invention Figures A to I are sectional views of essential parts of an element showing the formation process of an embodiment of the present invention.
まず八に示すように、デバイス形成済みのシリコン基板
１」二にシリコン酸化膜２を形成し、その上に第１層配
線層３を形成する。First, as shown in FIG. 8, a silicon oxide film 2 is formed on a silicon substrate 1''2 on which devices have been formed, and a first wiring layer 3 is formed thereon.
次にＢに示すように、第１層配線層３を含む全表面に、
ＣＶＤ法等により、酸化シリコンや窒化シリコン等の層
間絶縁層４を形成する。この際。Next, as shown in B, on the entire surface including the first wiring layer 3,
An interlayer insulating layer 4 of silicon oxide, silicon nitride, or the like is formed by CVD or the like. On this occasion.
眉間絶縁層４上には、第１層配線層の厚みに等しい段差
が形成される。A step is formed on the glabella insulating layer 4 to have a thickness equal to that of the first wiring layer.
この段差を除去して平坦化をばかるため、Ｃに示ずよう
に、眉間絶縁層４上に流動性のフォトレジスト膜５を平
坦になるように塗布し固化させたｆ＆、Ｄに示すように
、ドライエツチング手法等によりフォトレジストＩＩ！
５と層間絶縁Ｎ４を同じ速度でエツチングする。このエ
ツチングは、理想的には眉間絶縁層４上の段差が完全に
無くなるまで続けられるが２ フォトレジスト膜５の厚
みやエツチング速度のばらつき等により、Ｄに例示する
ように段差を残したままエツチングが終了する場合（３
）
もある。In order to remove this level difference and prevent flattening, a fluid photoresist film 5 is coated on the glabella insulating layer 4 so as to be flat as shown in C, and then solidified, as shown in D. Then, photoresist II!
5 and the interlayer insulation N4 are etched at the same rate. Ideally, this etching is continued until the level difference on the glabella insulating layer 4 is completely eliminated, but due to variations in the thickness of the photoresist film 5 and the etching speed, etching may be continued with the level difference remaining as shown in D. If ends (3
) is also available.
この後、已に示すように、素子表面に残留しているフォ
トレジスト
Ｆに示すように，酸化シリコンや窒化シリコン等の絶縁
物を付加して眉間絶縁層４の厚めを盛り」二げる。Thereafter, as shown in the figure, an insulating material such as silicon oxide or silicon nitride is added to increase the thickness of the glabellar insulating layer 4, as shown in the photoresist F remaining on the element surface.
次に，Ｇに示す，Ｌうに，層間絶縁層４上に有色不透明
薄膜７を形成する。この有色不透明薄膜７は，例えば真
空蒸着法等により形成したアルミニュウムの薄膜である
。引続き，この有色不透明薄膜７ーヒの段差の大きさを
光学顕微鏡により検査する。この段差が許容範囲を越え
ておれば，素子を廃棄処分にするか又は前述のＣの工程
にもどる。Next, as shown in G and L, a colored opaque thin film 7 is formed on the interlayer insulating layer 4. This colored opaque thin film 7 is an aluminum thin film formed by, for example, a vacuum evaporation method. Subsequently, the size of the step in this colored opaque thin film 7-hi is examined using an optical microscope. If this level difference exceeds the allowable range, the element is discarded or the process returns to step C above.
一方，段差が許容範囲内にあれば，ＩＩに示ずよりトポ
ール８を形成する。On the other hand, if the level difference is within the allowable range, the topole 8 is formed as shown in II.
最後に，、１に示すように，第２層配線層９を形成する
。この際，ｒ＠層間絶縁層の平坦化の不十分さにより第
２層配線層吐１−に段差１０が形成され（４）
るが、この段差の大きさは前記Ｇの工程において既に予
測済み゛であるから，第２Ｎ配線層９の断線に至るよう
な大きなものとなることはない。段差の許容値の具体的
な値は，形成すべき第２層配線層９の厚み等を考慮して
適宜な値に定められる。Finally, as shown in 1, a second wiring layer 9 is formed. At this time, a step 10 is formed in the second wiring layer 1- due to insufficient planarization of the r@ interlayer insulating layer (4), but the size of this step has already been predicted in the step G above. Therefore, there is no possibility that the problem will become so large as to cause a disconnection in the second N wiring layer 9. The specific value of the allowable value of the step difference is determined to be an appropriate value in consideration of the thickness of the second wiring layer 9 to be formed.
発明の詳細
な説明したように，本発明は，平坦化後の眉間絶縁層上
に有色不透明薄膜を形成し．該有色不透明薄膜」二の段
差を光学顕微鏡で検査して平坦化の度合を検査する工程
を含むように構成されているので，第２層配線層の断線
を有効に防ぐことができるという利点がある。As described in detail, the present invention forms a colored opaque thin film on the glabellar insulating layer after planarization. Since the structure includes a step of inspecting the level difference between the two layers of the colored opaque thin film using an optical microscope to check the degree of flattening, it has the advantage that disconnection of the second wiring layer can be effectively prevented. be.
図は，本配線の一実施例の形成工程を示す素子要部断面
図である。
１・・シリコン基板，２・・シリコン酸化膜。
３・・第１層配線層，４・・層間絶縁層，５・・フォト
レジスト膜，７・・有色不透明薄膜，８・・コンタクト
ホール、１０・・段差。
特許出願人 住友電気工業株式会社
代 理 人 弁理士 玉蟲久五部
（５）The figure is a sectional view of a main part of an element showing the formation process of one embodiment of this wiring. 1. Silicon substrate, 2. Silicon oxide film. 3. First wiring layer, 4. Interlayer insulating layer, 5. Photoresist film, 7. Colored opaque thin film, 8. Contact hole, 10. Step. Patent applicant Sumitomo Electric Industries Co., Ltd. Representative Patent attorney Gobe Tamamushi (5)
Claims (1)
を含む多層配線構造の形成方法において。 前記平坦化後の層間絶縁層上に有色不透明薄膜を形成し
、該有色不透明薄膜」二の段差を光学顕微鏡で検査する
ことにより、前記層間絶縁層の平坦化の度合を検査する
工程を含むことを特徴とする多層配線構造の形成方法。Claims: A method for forming a multilayer wiring structure including a step of planarizing an interlayer insulating layer formed on a first wiring layer. forming a colored opaque thin film on the interlayer insulating layer after the planarization, and inspecting the degree of planarization of the interlayer insulating layer by inspecting the second level difference of the colored opaque thin film with an optical microscope. A method for forming a multilayer wiring structure characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15847583A JPS6049650A (en) | 1983-08-29 | 1983-08-29 | Formation of multilayer interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15847583A JPS6049650A (en) | 1983-08-29 | 1983-08-29 | Formation of multilayer interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6049650A true JPS6049650A (en) | 1985-03-18 |
Family
ID=15672550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15847583A Pending JPS6049650A (en) | 1983-08-29 | 1983-08-29 | Formation of multilayer interconnection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6049650A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61501738A (en) * | 1984-04-04 | 1986-08-14 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | Double planarization method for multilayer metallization of integrated circuit structures |
| JPS63278242A (en) * | 1987-05-09 | 1988-11-15 | Fujitsu Ltd | Semiconductor device and method of testing flatness of surface thereof |
-
1983
- 1983-08-29 JP JP15847583A patent/JPS6049650A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61501738A (en) * | 1984-04-04 | 1986-08-14 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | Double planarization method for multilayer metallization of integrated circuit structures |
| JPS63278242A (en) * | 1987-05-09 | 1988-11-15 | Fujitsu Ltd | Semiconductor device and method of testing flatness of surface thereof |
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