JPS6049385B2 - Reception frequency display device - Google Patents

Description

[Detailed description of the invention]

The present invention aims to digitally display the reception frequency of a synthesizer receiver with high precision using an inexpensive configuration. In Japan, the intermediate frequency of FM receivers is 10.
7MH2, and frequency conversion is lower heterodyne. Therefore, when displaying the receiving frequency digitally, if the local oscillation frequency is counted and displayed as is, the displayed frequency will be higher than the receiving frequency at the intermediate frequency of 10.7 MH.
2, which does not indicate the received frequency. Therefore, in a conventional FM synthesizer receiver, a reception frequency display device is configured as shown in FIG. 1, for example. That is, 10 is a PLL, 11 is a VCO (voltage controlled variable frequency oscillation circuit), 14 is a presettable down counter, 15 is a phase comparison circuit, and 16 is a reference oscillation circuit. When the channel selection means 17 is set to, for example, 76MH2, the channel selection code is supplied to the counter 14, and the contents of the counter 14 are preset to [760]. Then, the oscillation signal of VCOII is divided into 11 by the frequency dividing circuit 12.
The frequency is divided by 4 and then supplied to the counter 14 as a count input, so that the contents of the counter 14 are decremented by [1] from [760]. Then, when the content of the counter 14 becomes [107] corresponding to the intermediate frequency 10.7MH2, this is detected by the detection circuit 18, and the counter 14 is again preset to [760] by the detection output. At the same time, an output pulse is taken out from the counter 14 during this presetting. Thereafter, this down-counting and presetting operation is repeated. Therefore, one output pulse is obtained from the counter 14 for every 653 input pulses (760-107);
This means that he has completed 1165 laps. Then, this frequency-divided pulse is supplied to the comparator circuit 15, and at the same time, a reference signal with a frequency of 25 kHz is supplied from the oscillation circuit 16 to the comparator circuit 15, and the comparison output is supplied to the VCOll as its control signal. Therefore, at a fixed time, the frequency of the output pulse of the counter 14 is equal to the frequency of the reference signal, so the oscillation frequency of the VCOll is 25 kHz x 653 x 4 = 65.3 MHz.
becomes. The oscillation signal of this VCOll is then supplied to the mixer circuit 3, and the received signal with a frequency of 76 MHz is converted into an intermediate frequency signal with an intermediate frequency of 10.7 MHz. Therefore, the reception state is at a frequency of 76 MHz. Also, at this time, the channel selection code [760] from the channel selection means 17 is
The received frequency 7 is supplied to the display element 2 through the decoder 1.
6.0MHz is displayed digitally. In this way, in the circuit of FIG. 1, the local oscillation signal is synthesized and the received frequency is digitally displayed. However, in this circuit, if the counter 14 is configured with 1 counter, the number of IC pins will increase.On the other hand, if it is configured with a binary counter, the channel selection code from the channel selection means 17 becomes a binary signal, so the decoder 1 , converts the binary signal to a BCD signal, and further,
It must be converted into a signal that drives the display element 2. Therefore, a display device as shown in FIG. 2 has also been considered. That is, a local oscillation signal is supplied from the local oscillation circuit 21 to the prescaler 22, and the local oscillation signal is supplied to the prescaler 22. The frequency is divided, and the frequency-divided signal is supplied to the AND gate 23. Further, when a reference pulse with a frequency of 500 Hz is supplied from the oscillation circuit 25 to the gate circuit 26 and the receiving frequency is changed,
The detection circuit 27 detects that the local oscillation frequency changes, and this! The detection output is supplied to the gate circuit 26, and only one reference pulse is taken out and supplied to the AND gate 23 only when the receiving frequency is changed. Therefore,
For example, if the receiving frequency is 76 MHz, the local oscillation frequency is 65.3 MHz, so the frequency of the prescaler 22 is 653 kHz.Therefore, from the AND gate 23, only when the receiving frequency is set to 76 MHz,
1306 pulses (=653k1500) are obtained. Then, this pulse is frequency-divided by 112 in the frequency dividing circuit 24 to produce 653 pulses, and this pulse is supplied to the presettable down counter 29 as count input 7, and this counter 29 also has a detection circuit. The output of 27 is supplied as a load signal, and the counter 29 is preset to [107] based on the designation of the preset circuit 28. Therefore, after counting, the contents of the counter 29 are [76
0] (=107+653). This count content is then supplied to the display element 2 through the decoder 1,
The received frequency of 76.0 MHz is displayed digitally. Note that the frequency dividing circuit 24 is for flickering prevention, and is reset before an output is obtained from the AND gate 23 when the reception frequency is changed based on the detection output of the detection circuit 27. Therefore, the display device shown in FIG. 2 does not have the same problem as the display device shown in FIG. 1. However, since this display device requires a high-speed prescaler 22, it becomes expensive as a whole. Further, although this display device is a static display, in the case of a dynamic display, pulse noise due to the dynamic display becomes a problem. In view of these points, it is an object of the present invention to provide a display device capable of digitally displaying a reception frequency with high precision using an inexpensive configuration. An example of this will be explained below. In FIG. 3, numeral 30 indicates a PLL for synthesizing a local oscillation signal, and in the VCO 3l, a local oscillation signal whose frequency changes between 65.3 and 79.3 MHz corresponding to the reception frequency is formed, This signal is supplied to the frequency converter 32, and an oscillation signal with a frequency of 90.5 MHz is taken out from the oscillation circuit 33. An alternating signal with a frequency that is the difference between the two signals is taken out from the converter 32, and this signal is sent to the frequency dividing circuit 34. The frequency is divided by 114 and then supplied to the programmable binary counter 35. Further, in the channel selection means 31, a channel selection code specifying the reception frequency is formed, and this code is supplied to the counter 35 to set its frequency division ratio A. In this case, this tuning code is a binary code,
When the reception frequency is 76MHz, it becomes [252],
The code signal decreases by [1] each time the receiving frequency increases by 100 kHz, and becomes [112] when the receiving frequency is 90 MHz. Therefore, the frequency division ratio of the counter 35 is 11252 to 11112 (N
=252 to 112). In this way, the signal from the frequency dividing circuit 34 is frequency-divided by the counter 35, and this frequency-divided signal is supplied to the phase comparison circuit 38, and at the same time, a reference pulse P6 with a frequency of 100 kHz is taken out from the reference oscillation circuit 36. This pulse P6 is transmitted to the frequency dividing circuit 39
The frequency is divided by 114 and then supplied to the comparison circuit 35, and the comparison output is supplied to the VCO 3l as its control signal. Therefore, in steady state, the frequency of the output of the counter 35 is
Since it is equal to the frequency of the output of the frequency dividing circuit 39, 25kHz,
The frequency of the output of the converter 32 at this time is N×4×
It becomes 25kHz. The oscillation frequency of the VCO 3l is the oscillation frequency of the oscillation circuit 33 minus the frequency of the output of the converter 32, so the oscillation frequency of the VCO 3l is 90.5.
MHz-N×100kHz. Then, the value of N is determined by the channel selection means 37 [252]
Since it changes by [1] between [112] and [112], the VCO
The oscillation frequency of 3l is set from 65.3 to 65.3 by the tuning means 37.
It changes in 100kHz units between 79.3MHz. Therefore, the oscillation signal of this VCO 3l is supplied to the mixer circuit 3 as a local oscillation signal, and the received signal has an intermediate frequency of 1
The frequency is converted to a 0.7 MHz intermediate frequency signal. The reception frequency display device 40 at this time is configured as follows in the present invention. That is, 41 indicates a tuning detection circuit, which is supplied with the tuning code from the tuning means 37, and when this code changes, that is, when the reception frequency is changed, the detection signal of this, is taken out. Further, 42 indicates a binary up counter, and since the maximum value of the channel selection code is [252], which is 8 bits in binary code, the counter 42 is also 8 bits. Then, the channel selection code from the channel selection means 37 is supplied to the counter 42 as a preset signal, and
The detection signal S1 of the detection circuit 41 is supplied to the counter 42 as a load signal. Furthermore, 43 indicates a BCD up counter, which includes a preset circuit 44 to [75
7] is supplied, and the detection circuit 4
1 detection signal S1 is supplied to the counter 43 as a load signal. Further, 45 indicates a maximum value detection circuit, to which the content of the counter 42 is supplied, and this content is detected as the maximum value [
255] (7-1), the detection signal S6 is extracted. Reference numeral 46 indicates a gate control circuit, to which the detection signals S5 of the detection circuits 41 and 45 are supplied, and the signal S1 from the control circuit 46 becomes ゜1゛.
A gate control signal S6 which becomes ゜゜0゛ is taken out by the signal S5. This signal S6 is supplied to the AND gate 47, and the oscillation pulse P6 of the oscillation circuit 36 is supplied to the AND gate 47, and the gate output is sent to the counter 42,
43 as a count input. Further, 48 is a decoder, and 49 is a display element. In such a configuration, at a certain receiving frequency, the tuning means 37 is operated to change the receiving frequency to, for example, 76r1V4HZ.
Suppose you set it to . Then, the reception frequency 76r1V4HZ is received from the channel selection means 37.
Correspondingly, the signal is supplied to the channel selection code counter 34 of [252], and becomes in a receiving state of 76 MHz. Then, this tuning code [252] is supplied to the counter 42 as a preset signal, and this tuning code [252]
The detection circuit 41 detects a change in the value, and the detection signal S1 is supplied to the counter 542 as a load signal, so that the contents of the counter 42 are preset to [252]. In addition, the counter 43 is supplied with [7] from the preset circuit 44.
57] is supplied, and the detection signal S1 is also supplied as a force output signal.
The contents of 3 are preset to [757]. Then, since the gate control signal S6 from the control circuit 46 becomes "l" due to the detection signal S1, the oscillation pulse P of the oscillation circuit 36
6 is supplied to the counters 42 and 43 through the AND gate 47, and therefore the contents of the counters 42 and 43 simultaneously increase by [1] from the preset values [252] and [757]. Then, when the content of the counter 42 reaches the maximum value [255], this is detected by the detection circuit 45, and the gate control signal S6 becomes ゜゜0゛ due to this detection signal S6. 43, and the counters 42 and 43 stop counting. Then, at the end of this, the counter 42 is [252]
Since we count three pulses P6 from [255],
The contents of the counter 43 are [760] (=757+3). And the contents of this counter 43 [760]
is supplied to the display element 49 through the decoder 48, and the reception frequency of 76.0 MHz is digitally displayed. In addition,
In this case, the signal pulse is supplied to the decoder 48 as a blanking signal, and while the counters 42 and 43 are counting, blanking is performed to prevent flickering. In the case of an arbitrary receiving frequency, if the corresponding tuning code is C, the count value Y of the counter 43 at the end of counting is Y=X+(2N-1)-C rx: Preset value (X=[NC:7-
This is the number of bits of the printer 42 (n=8). Then, the frequency of pulse P6 in PLL3O is 10
Since it is 0kHz, the display frequency of the display element 49 is Y×1
It becomes 00kHz. In this way, the reception frequency can be digitally displayed, but in this case, especially according to the present invention, the counters 42 and 43 convert between the binary code and the K1 code, so that the channel selection code is converted into a binary code. ■O display even if it is a code! I can do it. Furthermore, by presetting the counter 43, the offset between the channel selection code C and the count value (display frequency) Y can be corrected. Furthermore, the pulse P6, which serves as the count input for the counters 42 and 43, has a frequency as low as 1 so that flickering of the display does not become a problem, for example, 100k as described above.
Hz, high-speed operation counters 42 and 43 are not required, and the overall cost can be reduced. In addition, the frequency of the pulse P6 serving as the count input may be a frequency that does not cause a problem with display flickering, or the frequency may fluctuate. can be obtained easily. Furthermore, since the frequency of the pulse P6 may be low, it can be implemented as a C-MOS-1C. Further, since the counter 43 has a latch function, a latch circuit is not required. Furthermore, if it is a synthesizer receiver, just by changing the preset value of the counter 43, the A
It can be used as is in M receivers, foreign FM receivers, citizen band transceivers, etc. Furthermore, since the display is static and the counters 4S2 and 43 only operate for a short period when the reception frequency is changed, almost no noise is generated. FIG. 5 shows a specific example of how the display device 40 is connected. That is, the transistors Ql and Q2 constitute a monostable multipipulator 41A of the rise and fall trigger type, and the output thereof is supplied to the inverter 41B to constitute the detection circuit 41. In addition,
Transistor O is for resetting when power is turned on. Then, operate the channel selection means 37 to select the channel selection code (binary code).
When changing the channel selection code (code), the ? B
Since always changes from ゜"1" to "゜0" or from "0" to "1", this LSB is supplied to the multivibrator 41 as a trigger pulse. Therefore, the detection signal S1 is obtained from the inverter 41B. Also,
The binary counter 42 is composed of falling trigger type 4-bit binary up counters 42A and 42B connected in cascade. Then, when the content of this counter 42 reaches the maximum value [255], [25510]=[11111111]. ], and the output terminals of the counters 42A and 42B are all "1", so the detection circuit 45 is composed of an 8-input NAND gate, and the detected signal is taken out.
The CD counter 43 is a falling trigger type BCD.
The counter 43 is composed of up counters 43A, 43B and JK flip-flop circuits 43C, 43D.
A and 43B are connected in cascade, and the output of counter 43B is supplied in parallel to flip-flop circuits 43C and 43D, so that counter 43A counts the 1's digit (100 kHz of display frequency) of count value Y. , the counter 43B counts the tens digit (1 MHz digit), the counter 43B counts the tens digit (1 MHz digit), and the flip-flop circuits 43C and 43D correspond to the 100 digit (10 MHz digit). (The 100th place of count value Y is [7], [8],

[9], it can be realized by the flip-flop circuits 43C and 43D). Then, predetermined input terminals of the counters 43A and 43B and the input terminals of the flip-flop circuit 43C (7) J and K are
The preset circuit 44 is configured by being connected to the terminal at the level "゜1゛" and the J and K input terminals of the flip-flop circuit 43D are connected to its n terminal.
The gate control circuit 46 is a falling trigger type JK.
The flip-flop circuits 46A and 46B are connected in cascade, and are supplied with a pulse P6 as a clock pulse from the oscillation circuit 36.
The output signal S6 of No. 6 is synchronized with the pulse P6. Then, the inverter 47B is connected to the NAND circuit 47A.
are connected in cascade to form an AND gate 47, and the oscillation circuit 3
When the pulse P6 of 6 rises, the AND gate 47
is designed to open and close. Furthermore, as shown in FIG. 6, the display element 49 has seven segments a-
It is composed of anode common LEDs 49A to 49C with a receiving frequency of 100k.
The Hz, 1MHz, and 10MHz digits are displayed. That is, the outputs of counters 43A and 43B are BCD-
LED4 through 7 segment decoders 48A, 48B
9A, 49B, and the outputs of flip-flop circuits 43C, 43D are supplied to transistors 48C, 48D.
A predetermined segment of the LED 49C is supplied through the LED 49C, and the remaining segments are grounded. Further, the signal S5 from the NAND gate 45 is supplied to the blanking terminals of the decoders 48A and 48B through the inverter 48E. Therefore, this display device 40 performs the operation shown in the timing chart shown in FIG. That is, the chart in FIG. 4 shows the case where the receiving frequency is changed from 76.1 MHz to 76.0 MHz at an arbitrary time t1. Then, before the tuning time t1, the tuning code is [251] corresponding to the receiving frequency of 76.1MHz.
and is the LSB part 1 of its binary code. Further, since the transistor Q1 is on during normal operation, its collector output is "60", and therefore the signal S1 from the inverter 41B is "1". Furthermore, as will be clear from the description below, the flip-flop circuit 46A (7)
The Q output is 6'R2, and the signal S6 (Q output) from the flip-flop circuit 46B is "0", so the pulse P3 is not supplied to the counters 42 and 43. In this case, the contents of the counter 42 reached the maximum value [255], which led to the reception state of 76.1 KHz, so the contents of the counters 42 and 43 were [255] and [761], and , the signal S5 from the NAND gate 45 is "0". Then, if you perform a tuning operation to 76.0MHz at time t1, 76.0MHz
The channel selection code is [252] corresponding to MHz, and its LSB is "60". Therefore, due to the fall of this LSB, the signal S1 becomes ``0'' for a predetermined period and then becomes 6 "1" again.Then, due to the fall of this signal S1, the counter 42
, 43 are preset to [252], [757], and the flip-flop circuits 46A, 46B are cleared and their output becomes "0". Also, when the content of the counter 42 becomes [252], , which is not the maximum value, becomes S6 = ゜゜1゛.Then, at the time T2 of the falling edge of the first pulse P6 after that time, the flip-flop circuit 46A (:ri J, K inputs become "゜゜1゛"). Therefore, when the pulse P6 falls at time T2, its Q output becomes "1", and as a result, the J and K inputs become "0", so after that time the Q output becomes "1". Further, even if the pulse P6 falls at time T27, the input of the flip-flop circuit 46B(7)J is "0" at this time T2, so the signal S6 remains "0". At the falling edge of the next pulse P2 at time t, the flip-flop circuit 46B (7
) Since the J input pulse is "1", the signal S6 becomes "1". Therefore, the pulse P6 is supplied to the counters 42 and 43, and its content increases. Then, the three pulses P
6 is supplied to the counters 42 and 43, at the falling time ζ of the third pulse P6, the contents of the counter 42 become the maximum value [255] due to this falling.
S5=゜“0”, and the flip-flop circuit 46B is cleared at the fall of this signal S5, and S6=゜゜0.
It becomes ゛. Therefore, the counting of the counters 42 and 43 is completed, and since the content of the counter 43 is [760] at this time, the reception frequency of 76.0 MHz is displayed by the LEDs 49C to 49A. In addition, during the period Chi ~ ζ,
The contents of the counter 43 are changing, but during this period, the signal ■ passes through the inverter 48E to the decoder 48A,
48B, blanking is performed and therefore the frequency display does not flicker. According to this display circuit 40, during normal operation, there is no change in the signal, the signal only changes during the period t1 to ζ during which the display frequency changes, and almost no noise is generated. Moreover, the circuit 47A that processes the changing signal,
Among 47B, 41B, 48E and 46A, 46B, circuits 47A to 48E7 are packaged in one TTL-1C, and circuits 46A and 46B are also packaged in one TTL-1C.
Since they are packaged inside the IC, noise countermeasures can be taken simply by shielding these two ICs. In the above description, the counters 42 and 43 may be used as down counters, and the detection circuit 45 may be used as a minimum value detection circuit. In that case, for example, the oscillation frequency of the oscillation circuit 33 may be set to 51.
．． 2MHz, the tuning code is C, and the receiving frequency is 76M.
When it is Hz, it is [141], and it is increased by [1] for every 100kHz increase, and when the receiving frequency is 90MHz, it is [281], and the preset value by the preset circuit 44 is [619], and the detection circuit 45 is set to OR. As a circuit, the detected value may be set as (a)], and in this case, Y=X+C.

[Brief explanation of the drawing]

Figures 1 and 2 are system diagrams of a conventional example, Figure 3 is a system diagram of an example of this invention, Figure 4 is a diagram for explaining the operation, and Figure 5 is a connection diagram of an example of this invention. , FIG. 6 is a diagram of some of its elements. 30 is a P ratio, 41 and 45 are detection circuits, 42 and 43 are counters, and 49 is a display element.

Claims (1)

[Claims] 1. In a receiver that forms a local oscillation signal using a PLL and changes the frequency of the local oscillation signal using a tuning binary code, detects when the tuning binary code changes, and A binary counter is preset to the channel selection binary code by the detection signal, and a BCD counter is preset to a value corresponding to the offset between the channel selection binary code and the numerical value of the display frequency, and the binary counter and the above When the count input is supplied to the BCD counter and the content of the binary code reaches the predetermined value,
A reception frequency display device that stops the count input in response to a signal that detects this, supplies the contents of the BCD counter at this time to a digital display element, and digitally displays the reception frequency at the local oscillation frequency. .