JPS6047609B2 - multiplication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplication circuit that performs binary multiplication under clock control.

The n-bit multiplicand X and the m-bit multiplier Y of two's complement are expressed by the following equation.

X: - xn2・-1+, Σx, 2゛ ゜゜゜(1) Y
-ym2m-1+, Σxj2J...(2)] As a method for finding the product of the multiplicand x and the multiplier Y, PxY, a series method and a parallel method have been devised.

The former method has the advantage of requiring less hardware, but has the disadvantage of requiring m+n clocks to obtain the product. Although the latter method has the advantage of finding the product 5 at high speed, it has problems in terms of large amount of hardware and power consumption. On the other hand, when a multiplier circuit is connected to a mark processor or is fabricated on the same chip as a microprocessor, the specifications required for the multiplier circuit are not just high-speed operation, but also the ability to perform high-speed calculations using one instruction from the microprocessor. Perform the multiplication within the execution time,
Furthermore, the amount of hardware and power consumption of the multiplication circuit is small. The present invention was made in order to realize a multiplication circuit that satisfies the specifications shown above, and allows multiplication to be performed with fewer clocks than a series method, and with less hardware and power consumption than a parallel method. making it possible to execute.

Examples of the present invention will be described below.

The following explanation will be given by taking as an example the case where both the multiplicand X1 and the multiplier Y1 are 8 bits.

In other words, X and Y are each expressed as ゛.

Here, X7 and y7 are sign bits of 2, which are 1 when representing a negative number and O when representing a positive number. Equation (4) can be expanded as shown below. Therefore, when the product P=XY is calculated using equation (5), it becomes k←oKlU.

Here it is.

Therefore, to find the product P, use equation (6). After calculating the partial product Pk, the partial products Pk may be added as shown in equation (5). The above is called Booth's algorithm. In the present invention, the partial products of equation (6) are obtained every clock, the results are added, and the results are accumulated.
Results can be obtained in 4 clocks.

FIG. 1 is a diagram showing an embodiment of the present invention. The multiplicand x shown in equation (3) is latched into register 1. Also, the multiplier Y shown in equation (4) is the shift register 2,
It is latched into shift register 3. The latching timing is performed by the clock a generated by the timing generation circuit 4, and is latched at timing T as shown in FIG. It will be held in Shift; Tre register 2 is a 5-bit shift register, and Y out of the multiplier Y shown in equation (4)
7, y5, y3, yl and y-1, which is identically 0, are arranged as [Y7, y,, y3, yl, y-1] at timing T. is latched. Shift register 3 is
It is a 4-bit shift register, and of the multiplier Y shown in equation (4), ~Y69y49y29yO) [Y6!
Y49y22YO], timing T. is latched. Shift register 2, shift register 3
, the clock b is input as a shift clock from the timing generation circuit 4, and the timing Tl shown in FIG.
, T2, and T3. Therefore, considering the set of 3 bits (LSB of shift register 2, U of shift register 3, bit one higher than the LSB of shift register 2), timing TO9Tl9T2
9T3 (y-19y09y1) 9(Yl9y29y3
)9(Y3, y4, y5), (Y5, y6, y7) are obtained. These outputs and the output of register 1, ie, multiplicand X, are connected to partial product generation circuit 5. An example of the configuration of the partial product generation circuit 5 is shown in FIG. In the partial product generation circuit shown in FIG. 3, (Y2k+1, y2,
,y2k-1) is (0,0,0) or (1,1,
1), the output Dk becomes O.

(Y2k+1,y2k,y2k-1) is (0,0,1)
Alternatively, when (0, 1, 0), the output D becomes X. (
Y2k+1, y2k, y21. -1) is (0,1,1)
When , the multiplicand x is shifted to the left by 1 bit and output, so the output Dk becomes △. (Y2k+,,Y2!.,
When Y2k-1) is (1,0,0), the multiplicand X is inverted and shifted one bit to the left. Therefore, the output Dk
becomes.

(Y2k+1,y2k,y2!.-1) is (1,0,1
) or (1, 1, 0), the multiplicand X is inverted and output, so the output Dk becomes -A1 1 .

To summarize the above, the output Dk of the partial product generation circuit 5 is expressed as follows.

Here, Ck is v't~,, J4=-i deception? rl-. Akebono A
There is 〒 found by 16hn, (Y2k+19y2k9
y2k-1) is (1,0,0), (1,0,1), (1
, 1, 0).

Therefore, if we decide to correct these times by adding 1 and correct the weight 22k using another method, we get (6
) and (9) are the same. In other words, Booth's algorithm can be applied. Output C of partial product generation circuit 5
k outputs 1 or O according to equation (1a), which is used for the above-mentioned corrections. These corrections will be described later. Timing T.

, Tl, T2, T3, the output of the partial product generation circuit obtained according to equation (9) is a 9-bit long CLA (Carr
The adder 6, the 7-bit register 7, the 3-bit shift register 8, and the 3-bit shift register 9 perform cumulative addition as shown below. At timing TO, the contents of register 7 are reset to O by clock a. Also, at the same timing, the input of the partial product generation circuit 5 is (Yl, yO, y-
1), from the output terminal Dk and the output terminal Ck, (JO-y1
\1J0J-1ノ is output.

On the other hand, the output terminal Ck is connected to the carry input of the CLA adder. Therefore, until timing T1, C
The LA adder 6 performs the addition of N'MariNa'1A~Me→I)-\J-1IJVUJ.

A3) Equation (6) is equal to the value when k=0. That is, the partial product P. is found. As shown in FIG. 4, the partial product o has 9 bits, but at timing T1, the LSB is shifted into shift register 8, and the digit one higher than 5SB is shifted into shift register 9 by clock b. . The upper 7 bits are also latched into register 7 by clock b. At timing T1,
Since the input of the partial product generation circuit 5 is (Y3, y2, yl), the output from the output terminal Dk and the output terminal C is performed according to equations (9) and QO), respectively.
Ha-'1A) 1:Y
3(1-y1 ”Y2ノ
, -5 are output.

On the other hand, the output terminal C, is connected to the carry input of the CLA adder 6, and the data in the register 7 is sign-extended by 2 bits and inputted to the CLA adder. Therefore,
Until timing T2, CLA adder 6
H. J Ueyama-? 11n) 67) - M11& (Mu ＾vゞ5上YV'2 (P1 is set as k=1 in equation (6)) is added.

As shown in Figure 4, the value obtained by the equation σ6)? B
The weight of is f. Also, partial product P. (7) Since the LSB and the bit one higher than the LSB are stored in shift register 8 and shift register 9, respectively,
This means that the process shown in FIG. 4 has been executed just before timing T2.

At timing T2, in the same way as before, the CLA adder 6
Of the outputs, the LSB is sent to shift register 8;
The next higher-order bit is shifted into the shift register 9 by clock b. The upper 7 bits are also latched into register 7 by clock b. At timing T2, the input of the partial product generation circuit 6 is (Y5,
y4, y3), output terminals DIC and C output according to equations (9) and 00, respectively.

Then, in the same way as before, the CLI'' adder 6 performs the addition of ``1'' (P2 is k=2 in equation (6) and J Bar Co.).

On the other hand, P. Since the lower 4 bits of +P1 have already been stored in shift registers 8 and 9, the process shown in FIG. 4 has been executed just before timing 3.

At timing T3, the same thing as before is done, so by just before timing T4, as shown in FIG. 4 has been executed, that is, equation (5) has been executed, and the product P=
Find X-Y.

Here, the product P is 1? υ, at timing T4, 4, Z2, Z4 are in the order [Z4, Z2, 4] in the shift register 8, and Zl, 4, 4 are in the order [Z4, Z2, 4] in the shift register 9.
Z5, Z3, Zl].

Therefore, shift registers 8 and 9 and output buffer 1
By adjusting the connection between 0 and 0, the values shown in equation (20) can be obtained from the output terminal of the output buffer 10 in the correct order. The above explanation was given using the case of 8 bits x 8 bits as an example, but in the case of other bit numbers as well,
A multiplier can be similarly constructed by adjusting the register, the partial product generation circuit, the CLA adder, the bit length of the output buffer, and the clock b that is the output of the timing generation circuit.

4. As explained above, according to the present invention, for example, 8 bits x 8 bits multiplication requires 4 clocks, and generally when the multiplicand is n bits and the multiplier is m bits, the product of both is calculated using the field clock. be able to. Also, the data flow in one clock is 5 register Q
Partial product generation circuit-(>CLA adder, and CL
Since the A adder only performs the calculation of two numbers, the clock interval can be reduced by an N-channel MOS process.
It is possible to make it several tens of nanoseconds. Therefore, it is possible to perform multiplication in several hundred nanoseconds. On the other hand, when multiplication is performed using a serial multiplication method in which the multiplicand is n bits and the multiplier is m bits, n+m clocks are required.
That is, the multiplier of the present invention can perform 52 (n+m) multiplications in a time of 1'L- compared to a multiplier using a serial multiplication method.

Furthermore, since the partial product generation circuit and the CLA adder are used in a time-sharing manner, the amount of hardware and power consumption are also reduced compared to the parallel method.

For example, the MMI multiplier (model number 67558) uses Booth's algorithm to perform 8-bit x 8-bit multiplication in parallel, and has approximately 680 gates.
On the other hand, the 8-bit x 8-bit multiplier according to the present invention requires only about 450 gates. As described above, according to the present invention, it is possible to execute multiplication at high speed with a relatively small amount of hardware. A multiplication circuit suitable for being fabricated on a chip can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the output of the timing generation circuit when executing 8 bit x 8 bit, and FIG. 3 is a diagram showing the part of FIG. 1. FIG. 4, a diagram showing an example of the configuration of a product generation circuit, is 8b1t×
FIG. 3 is a diagram showing the flow of data when performing 8-bit calculations.

1, 7...Register, 2,3,8,9...Shift register, 4...Timing generation circuit, 5...Partial product generation circuit, 6...CLA adder, 10... output buffer.

Claims (1)

[Claims] 1 Negative numbers are expressed in 2's complement in the first register that temporarily stores an n-bit multiplicand, and negative numbers are expressed in 2's complement in m-bit multiplier (m is an even number).
a first shift register that temporarily stores bits having a weight of l{l=0, 1, ..., (m-2)/2};
In the bit length multiplier Y, 2^2l^+^1{l=0, 1
, ..., (m-2)/2}, and a second shift register that temporarily stores bits with a weight of 2^-^1 and always 0, and an output X of the first register,
LSB (least significant bit) of the first shift register
Output y_2_k, LSB of said second shift register
The output y_2_k_-_1 and the bit output y_2_k_+_1 one higher than the LSB are input, and D_k=(y
_2_k_+_1+y_2_k-2y_2_k_+_1
)X-C_kC_k=y_2_k_+_1(1-y_2
Partial product D_k found by ＿k・y_2_k_-_1)
, a partial product generation circuit that outputs carry C_k, and a CLA (Car
ryLookAhead) adder, a third shift register that receives the LSB of the output of this CLA adder, a fourth shift register that receives most of the bits higher than the LSB, and other bits. a second register whose input is input and whose output is another input of the CLA adder; an output of the CLA adder, an output of the third shift register, and an output of the fourth shift register; an output buffer as an input;
It has a circuit that outputs load and shift timing to the second register and the first, second, third, and fourth shift registers, and performs multiplication under clock control.
A multiplication circuit characterized by executing multiplication in m/2 clocks and obtaining multiplication results in parallel.