JPS6046745B2 - Memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access method, for example, a memory access method for detecting a write address violation when storing data from a data channel or the like to a main memory in a central processing system of an electronic exchange. .

Conventional methods for memory protection include, for example, providing a memory lock for each block of memory, preparing a key on the central processing unit or data channel side that requests writing, and
There is a method of protecting the memory by setting a match condition in the main memory, and if the condition is not satisfied, writing is prohibited and a protection error is treated.

If there is a store from the data channel, writing is prohibited and protect error information is sent to the data channel.
A master key is prepared for times when it is necessary to write to the system area when reporting data channel operation results, etc., regardless of the memory lock condition. Another method is to protect the divided blocks by giving them memory protection information.
In order to ignore the protect information, there was also a method of preparing a special means for issuing a signal specifying protection ignore. However, the former method has the disadvantage of requiring a large amount of hardware such as interface lines and key match circuits for key information, while the latter method requires hardware for sending out protection ignore designations, and This method has drawbacks such as requiring one additional memory cycle in addition to normal memory access for setting the protection ignore designation in a memory device.

An object of the present invention is to appropriately detect and judge write address violations in this type of memory access, and to perform write operations based on the results of the detection and judgment, by devising the combination of the protected memory and the means for determining whether writing is possible. The purpose is to allow the accessing device to decide on measures such as prohibition, thereby increasing operational flexibility and increasing practicality.

In the present invention, when a write operation from the central processing unit or data channel device accesses a specific area divided into a predetermined number of words on the main memory, a protect memory provided separately from the main memory is accessed. A detection circuit is provided in the main memory control section of the central processing unit to check whether the output data is ROJ or RlJ and determine whether it is a protected area. means for returning a signal detected by the circuit, and means for determining whether or not the writing is valid based on the signal returned from the means within the accessed device, and based on the result of the determination. There is provided a memory access method characterized in that the accessing device side can decide whether or not to prohibit write-in.

An embodiment of the invention will be described with reference to FIGS. 1 and 2. FIG.
At the input terminal 7 of the protect memory 9, AO, Al
, . . . A5 is an address giving a protect block, and is the upper bit of the address from the central processing unit 1 or data channel device 21 when accessing the main memory 41, 42, . Ru. Here, the address register 4 in the main memory control circuit 2 of the central processing unit 1 receives the central processing unit usage permission signal 3 and outputs the address signal 5, and the address register 23 in the data channel 21 outputs the data channel usage permission signal 22. Receive address signal 24
Output. The gate system 6 includes, for example, gates 600, 6
01, . . . 609, 610, . . . 614, 615, these are address signals AD for the main memory device.
O,ADl,...Oil9,AD10...AD
They correspond to ADl4 and ADl5, respectively. The upper 6 bits of this address signal ADlO, ADll, ... ADl
5 is connected to the input terminal 7 of the protect memory 9 with AO, Al, .
...Given as A5. Separately protected memory 9
Write enable (WE), chip enable (CE), and data input (DI) signals are input to the input terminal 8 of the. DI and WE instruct protect set and write to protect memory, and are used when providing protect information to protect memory. In this way, protect information is held in the protect memory 9. The output 10 of the protect memory 9 is the gate 14
, but the other input S3 of gate 14 is “write”.
The order is given through gate 13 as a memory write instruction 11 from the data channel or as a memory write instruction 12 from the central processing unit.

The output of the gate 14 is supplied to the gate 17, and the other input 16 of the gate 17 is a protection invalidation signal S4, which is a signal used when the central processing unit ignores protection.
Thus, protect memory 9, gate 14, and gate 17 form a detection circuit. The output of the gate 14 is also given to the data channel determination circuit 25 as protect information S5 to be sent back to the data channel. The determination circuit 25 determines whether writing is valid or not. The output of the gate 17 is given to the interrupt circuit 18 and the like as protection information S6 for processing within the central processing unit. The output of the gate 6 in the main memory device control circuit 2 of the central processing unit 1 is connected to the main memory devices 41, 42, . . . . The main storage device consists of units 41, 42, . . . each having 64 memory blocks of 1 kiloword, for example. Each memory block of the main storage devices 41, 42, . . . corresponds to one section of the protect memory 9. The operation will be explained with reference to FIG.

First, regarding the memory access of the central processing unit 1, a method of detecting a write address violation when a protected area is accessed will be described. When the memory of a certain memory block is accessed, data S5 is output from the protect memory 9 to the accessed address. \
Assume that RlJ is protected and ROJ is unprotected. Since the memory is not destroyed when reading the memory, a write instruction is given as an input to the gate 14, and when reading, the output of the gate 14 is set as ROJ. Normally, protection is invalidated by RO, so when a write instruction to a protect block is issued, the output of gate 17 becomes RlJ, and protection error detection interrupt processing begins. Following this interrupt processing, error processing, failure detection, etc. are performed to return to normal processing. If it is necessary to write regardless of memory protection, by setting protection invalidation to RlJ, information in the protected memory is ignored and writing to the memory is performed. Next, a method of memory protection in the data channel 21 will be explained.

From the data channel 21 to the main storage devices 41, 42, . . .
When accessing, the address from the data channel 21 is input to the protect memory 9, and it is determined whether the memory block corresponding to the address from the data channel 21 is a protected area. If it is a memory store, gate 14 is activated, and if it is a protect area, a signal 20 is used to report to the data channel that it is a memory store to the protect area as a write address violation. Although not shown, the data channel ignores protect error information when memory protection is not necessary or when memory store must be performed regardless of memory protection. If protection is necessary, if a write address violation is detected in a report from the central processing unit, memory store is prohibited and memory protection error processing is started. Note that in the above description, the protect memory is described as being placed in the central processing unit, but it is also possible to place the protect memory in the memory control section of the main storage device instead.

According to the present invention, the present invention is based on the existence of a detection circuit that determines whether a write operation from the central processing unit and the data channel is an access to a specific area divided into a predetermined number of words on the main memory. Therefore, the detection judgment of write address violation in this type of memory access is performed properly,
Measures such as write prohibition based on the result of the detection determination can be determined on the accessed device side, increasing operational flexibility and increasing practicality.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram for explaining a memory access method as an embodiment of the present invention, and FIG. 2 is a circuit diagram for explaining the operation of FIG. (Explanation of symbols), 1...Central processing unit, 2...
・Main memory control circuit of central processing unit, 4...address register, 6...gate, 9...
・Protect memory, 13, 14, 17... Gate, 21 ・Data channel, 23... Address register, 25... Judgment circuit, 41, 42...
...Main memory.

Claims (1)

[Claims] 1. When a write operation from the central processing unit or data channel device accesses a specific area divided into a predetermined number of words on the main memory, a protect memory provided separately from the main memory is accessed and the output is Data “0”
” or “1” and determines whether the area is a protected area or not, is provided in the main storage control section of the central processing unit, and the detection circuit detects a device that has accessed the main storage. and means for determining whether or not the writing is valid based on the signal returned from the means in the accessed device, and prohibiting writing based on the result of the determination. The accessing device side can decide whether or not to do so.
A memory access method characterized by: