JPS6046625A - Echo canceller - Google Patents

Echo canceller

Info

Publication number
JPS6046625A
JPS6046625A JP15413683A JP15413683A JPS6046625A JP S6046625 A JPS6046625 A JP S6046625A JP 15413683 A JP15413683 A JP 15413683A JP 15413683 A JP15413683 A JP 15413683A JP S6046625 A JPS6046625 A JP S6046625A
Authority
JP
Japan
Prior art keywords
echo
adder
multiplier
echo canceller
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15413683A
Other languages
Japanese (ja)
Other versions
JPS6317371B2 (en
Inventor
Masaki Kobayashi
正樹 小林
Yoshio Ito
伊藤 良生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP15413683A priority Critical patent/JPS6046625A/en
Publication of JPS6046625A publication Critical patent/JPS6046625A/en
Publication of JPS6317371B2 publication Critical patent/JPS6317371B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/20Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
    • H04B3/23Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To increase an echo suppressing effect and to reduce power consumption by deriving an approximate form to the trasmission function of an echo cource and constituting a circuit generating said transmission fuction by an RC primary circuit, a multiplier and an adder. CONSTITUTION:An input signal X(t) is inputted to a course passing through the multiplier 12-1, the RC primary circuit network consisting of a resistor 10 and a capacitor 11 and a course passing through a multiplier 12-1 and outpus of respective courses are added by an adder 13 to generate a false echo Y'(t). After being inverted at the phase, the false echo Y'(t) is added to an echo Y(t) by an adder 5 and erased. The zero point of the transmission function of an echo canceller 18 can be made to coincide with the zero point of the transmission function of the echo course by controlling the application of tap factors d0, D1.

Description

【発明の詳細な説明】 (技術分野) 本発明はディノタル加入者線双方向伝送系における2線
、4線変換部で生じる4線側送信部から受信部へ漏えい
する信号を消去するエコーキャンセラに関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an echo canceller that cancels signals leaking from a 4-wire side transmitting section to a receiving section generated in a 2-wire to 4-wire conversion section in a dinotal subscriber line bidirectional transmission system. .

(従来技術) 最近集積回路技術の飛躍的進歩により各種装置のディジ
タル化が行われている。電話の加入者線に対しても従来
の音声帯(4kHz帯)を主としたアナログ伝送方式ふ
らより広いサービスをめざす高速のディジタル伝送方式
への移行が各方面で検討されている。第1図に従来のデ
ィソタル加入者線双方向伝送系のブロック構成を示す。
(Prior Art) Recently, various devices have been digitized due to dramatic advances in integrated circuit technology. For telephone subscriber lines, various fields are considering a transition from the conventional analog transmission system, which mainly uses the voice band (4 kHz band), to a high-speed digital transmission system that aims to provide a wider range of services. FIG. 1 shows a block configuration of a conventional digital subscriber line bidirectional transmission system.

同図において1は4線側入力端、2は4線側出力端、3
はハイブリッド回路、4はエコーキャンセラの擬似エコ
ー発生回路、5は加算器である。4線側入力端1から出
力端2へ漏えいするエコーと、擬似エコー発生回路4の
出力を位相反転して加算器5によって加算することによ
り前記エコーを強制的に消去するものである。第2図は
従来のエコーキャンセラの擬似エコー発生回路を示す。
In the figure, 1 is the 4-wire side input end, 2 is the 4-wire side output end, and 3 is the 4-wire side input end.
4 is a hybrid circuit, 4 is a pseudo echo generating circuit of an echo canceller, and 5 is an adder. The echo leaking from the input terminal 1 on the 4-wire side to the output terminal 2 and the output of the pseudo echo generating circuit 4 are inverted in phase and added by an adder 5, thereby forcibly canceling the echo. FIG. 2 shows a pseudo echo generating circuit of a conventional echo canceller.

同図において7−1+ 7−2 y・・l 7−(N−
1)は遅延素子、8−1゜8−2.・・・、8−Nは係
数り。、hl、・・h(N−1)を持つ乗算器、9は加
算器である。4線側送信信号x(t)は遅延素子7−1
へ入力し、順次遅延素子7−2.・・。
In the same figure, 7-1+ 7-2 y...l 7-(N-
1) is a delay element, 8-1°8-2. ..., 8-N is a coefficient. , hl, . . h(N-1), and 9 is an adder. The 4th line side transmission signal x(t) is transmitted through the delay element 7-1
and are sequentially input to delay elements 7-2. ....

7−(N−1)を通って遅延されると同時に、各遅延素
子の間から出ているタップを通り各々対応する乗算器8
−1.・・、8−Nで各係数hk(k=0 、・、N−
1)が掛けられ、その結果を加算器って加えることによ
り擬似エコー?(t)が生成される。従来の擬似エコー
発生回路4は、アナログ回路で構成する場合にはアナロ
グ遅延線が必要となpLSI化には不向きであり、又デ
ィノタル回路で構成するには前述し/ζ如く加入者線の
高速ディノタル化を考慮すると、その演算処理速度の高
速化や、低消費電力の実現に問題があった。
7-(N-1), and at the same time passes through the taps coming out between each delay element and the corresponding multiplier 8.
-1. . . , 8-N, each coefficient hk (k=0 , ., N-
1) is multiplied and the result is added using an adder to create a pseudo echo? (t) is generated. When the conventional pseudo-echo generation circuit 4 is configured with an analog circuit, it is not suitable for pLSI because it requires an analog delay line, and when it is configured with a dinotal circuit, it is necessary to use a high-speed subscriber line as described above. Considering digitalization, there were problems in increasing the processing speed and achieving low power consumption.

1次回路網、乗算器、および加算器とにより処理速度が
速く、消費電力が小さり、LSI化に適したエコーキャ
ンセラを提供することにある。以下本発明を図面を用い
て詳細に説明する。
The object of the present invention is to provide an echo canceller that has high processing speed, low power consumption, and is suitable for LSI implementation due to the primary circuit network, multipliers, and adders. The present invention will be explained in detail below using the drawings.

(発明の構成〕 エコー経路と擬似エコー経路の信号を相殺するエコーキ
ャンセラにおいて、エコー打消誤差が最小となるような
係数を持つ2つの乗算器の一方に人力信号を加え、他方
にはRC1次回路網を介して入力信号を印加し、両乗算
器の出力を加算する加算器と、4線側出力へのエコーと
前記加算器の出力を相殺する手段を有するエコーキャン
セラである。
(Structure of the Invention) In an echo canceller that cancels signals on an echo path and a pseudo-echo path, a human input signal is applied to one of two multipliers having coefficients that minimize the echo cancellation error, and an RC primary circuit is applied to the other multiplier. This echo canceller has an adder that applies an input signal via a network and adds the outputs of both multipliers, and means that cancels the echo to the output of the 4-wire side and the output of the adder.

(実施例の説明〕 第3図は本発明の一実施例を示す回路図である。(Explanation of Examples) FIG. 3 is a circuit diagram showing one embodiment of the present invention.

同図において10はR(Ω〕なる抵抗、11はC(F)
なるコンデンサ、12 、 t 12−2は係数d。l
 d、なる乗算器、13は加算器、14は乗算器、15
は累積加算器、16は係数αなる乗算器、17−、。
In the same figure, 10 is a resistance R (Ω), and 11 is C (F).
capacitor, 12, t12-2 is the coefficient d. l
d, a multiplier, 13 an adder, 14 a multiplier, 15
is an accumulation adder, 16 is a multiplier with coefficient α, 17-, .

17−2はR(Ω)なる加入者線の終端抵抗、18はエ
コーキャンセラである。第3図に示すエコー経路の伝達
関数H(S)は (1)式で表わせる。ここでSは複素周波数、ZIN(
sっは2線、4線変換部より2線側(加入者線側)をみ
たインピーダンスである。又伝達関数I((S)に対応
する時間関数h(t)とすると h(t) −L” [l’H(S) :) ・−・・・
・・・・・・・・ (2)で表わされる。ここでt −
]は逆ラうラス変換を示す。4線側入力信号をx(t)
とするとエコーy’(t)は y(t) −x(t) * h(t) ・・・・・・・
・・・・・・・・ (3)となる。*はたたみ込み演算
を示す。同時に入力信号X(t)はエコーキャンセラ1
8にも入力する。
17-2 is a terminating resistor of the subscriber line R (Ω), and 18 is an echo canceller. The transfer function H(S) of the echo path shown in FIG. 3 can be expressed by equation (1). Here S is the complex frequency, ZIN(
s is the impedance seen from the 2-wire/4-wire converter to the 2-wire side (subscriber line side). Also, if the time function h(t) corresponding to the transfer function I((S) is h(t) -L"[l'H(S) :) ・-...
...... It is expressed as (2). Here t −
] indicates an inverse lath transformation. The input signal on the 4-wire side is x(t)
Then, the echo y'(t) is y(t) -x(t) * h(t) ・・・・・・・・・
......(3). * indicates a convolution operation. At the same time, the input signal X(t) is echo canceller 1
Also enter 8.

この入力信号x(t)はエコーキャンセラ18内におい
て次のように処理され、擬似エコー?(t)を発生ずる
。入力信号x(t)は乗算器12−1を通る経路及び抵
抗10とコンデンサ11より成るRCI次回路網と、乗
算器12−2を通る経路に入力し、各経路の出力が加算
器13によって加え合わされ、擬似エコー?(t)が発
生する。該擬似エコー9(t)U位相反転後、加算器5
でエコー3/(t)と加算されエコーy(t)が消去さ
れる。4線側出力端2に示す信号e(t)は e(t) −y(t) −9(t) ・・・・・・・・
・・・・・ (4)でありエコー打消誤差を示している
。以下本発明の原理について説明する。
This input signal x(t) is processed in the echo canceller 18 as follows, and is processed as a pseudo echo? (t) is generated. The input signal x(t) is input to a path passing through a multiplier 12-1, an RCI circuit network consisting of a resistor 10 and a capacitor 11, and a path passing through a multiplier 12-2, and the output of each path is inputted by an adder 13. Added together, pseudo echo? (t) occurs. After the pseudo echo 9(t)U phase inversion, the adder 5
is added to echo 3/(t), and echo y(t) is deleted. The signal e(t) shown at the output terminal 2 on the 4-wire side is e(t) -y(t) -9(t) ...
...(4), which indicates the echo cancellation error. The principle of the present invention will be explained below.

2線、4線変換部より2線側(加入者線側)をみたイン
ピーダンス関数ZIN(S)l/1:次式で表わされる
Impedance function ZIN(S)l/1 viewed from the 2-wire/4-wire converter to the 2-wire side (subscriber line side) is expressed by the following equation.

・・・・・ (5) ここでz −(7’ l )2 f口 ct−]−(R+ G −。・・・・・・(5) Here z −(7’ l )2 f mouth ct-]-(R+G-.

LC Q−qp R3二V江 C γ−(R+5L)(G+SC):加入者線の伝搬定数R
,L、C,G :加入者線の一次定数l:加入者線路長 で渡る。従ってエコー経路の伝達関数H(s)は(1)
LC Q-qp R32VeC γ-(R+5L)(G+SC): Propagation constant R of subscriber line
, L, C, G: Primary constant of subscriber line l: Crossed by subscriber line length. Therefore, the transfer function H(s) of the echo path is (1)
.

(5)式より ・・ ・・・・・ (6) となる。実際の線路では = (−’−)2S (S + 2α) −・・・・・
・・・・・・・ (7)πU (7)式とみなせる。(7)式を用いて(6)式を以下
の様にについて示す。
From equation (5)... (6). In the actual line = (-'-)2S (S + 2α) -...
...... (7) πU It can be regarded as formula (7). Using equation (7), equation (6) is shown as follows.

00)式が虚根となる最小のkの値である。更に(8)
式において Nは T2(S)=82+2αS+(7k)2 −・・・・・
・・・・・ αΦαゆ式が虚根となる最小のkの値であ
る。更に(1Q式において ・・・・・・ (1す 〜πU となる。ただし09式の導出においてθに一7k。
00) is the minimum value of k for which the expression is an imaginary root. Furthermore (8)
In the formula, N is T2(S)=82+2αS+(7k)2 −・・・・
... αΦα is the minimum value of k for which the formula has an imaginary root. Furthermore, in formula 1Q... (1s~πU. However, in the derivation of formula 09, θ is -7k.

k≧Nなる近似を行っている。以上より(8) 、 (
1◇。
An approximation is made where k≧N. From the above (8), (
1◇.

(12,90式を用いれば(6)式は次のようになる。(If formulas 12 and 90 are used, formula (6) becomes as follows.

・・・・・・・・ 0Q 」二式において とおくと となる。(旧式は更に次式のように展開される。・・・・・・・・・0Q ” In the second formula And then becomes. (The old formula is further expanded as follows.

・・・−・ (埒 αつ式においてP□(s)、P2(s)が実根を有しな
い加入者線路長に対しては P、(s) = P2(s) = 1 − ・−−・ 
(ハ)であるゆえ(19)式は となる。即ちエコー経路の伝達関数H(S)は近似的に
S平面負の実軸上の1極、1零点を有する関数形となっ
ている。一方第3図に示すエコーキャンセラー8の伝達
関数H(S)は (イ)式で表わせる。即ちS千面負の実軸上に極−61
零点−do+dtを有している。つまりタップ係数d。
・・・−・ (In the α formula, P□(s) and P2(s) have no real root for the subscriber line length, P,(s) = P2(s) = 1 − ・−−・
Since (c), the equation (19) becomes. That is, the transfer function H(S) of the echo path has a functional form approximately having one pole and one zero point on the negative real axis of the S plane. On the other hand, the transfer function H(S) of the echo canceller 8 shown in FIG. 3 can be expressed by equation (A). In other words, the pole -61 is on the real axis of the S thousand-sided negative
It has a zero point -do+dt. In other words, tap coefficient d.

。 oCR dlを適応制御することによりエコー経路の伝達関数H
(S)の零点に一致させることができる。エコーキャン
セラー8の極の位置は−1に固定されてR いるが、この固定極は適用される加入者線路の最大長の
場合の極の位置に固定しておけば、それ以下の加入者線
路長に対してHS/N比の劣化にはならない。次にタッ
プ係数d。、dlの適応制御の方法について示す。まず
評価関数Jを 1− ・・・・・・−・・ (ト) J=Σe2(t) とする。ここで−は時間平均を示す。このとき最大傾斜
法を用いたタップ係数d。+dlの更新アルゴリズムは
、次のようにして導出される。ν回目の(ν) (ν) 更新後のタップ係数値をd。 、dl とすれば・・・
・・・・・ (財) である。ここでαは1回目のタップ係数の更新量とガー
るので(ハ)式を(ハ)式に代入すればり、プ係数の更
新アルゴリズムは となる。ただしΔd−αe(t) x(t) rΔd、
=αe(t) P(t)(ハ)式で示されるタ、、、f
係数の更新アルゴリズムを用いた制御系が第3図に示す
エコーキャンセラである。
. By adaptively controlling oCR dl, the echo path transfer function H
It is possible to match the zero point of (S). The pole position of the echo canceller 8 is fixed to -1 R, but if this fixed pole is fixed at the pole position for the maximum length of the subscriber line to which it is applied, then the subscriber line of less than The HS/N ratio does not deteriorate with respect to the length. Next, tap coefficient d. , dl will be described. First, let the evaluation function J be 1- . . . (g) J=Σe2(t). Here, - indicates the time average. At this time, the tap coefficient d using the maximum slope method. The update algorithm for +dl is derived as follows. The tap coefficient value after the νth (ν) (ν) update is d. , dl...
... (goods). Here, α is equal to the first update amount of the tap coefficient, so by substituting equation (C) into equation (C), the update algorithm of the tap coefficient becomes as follows. However, Δd−αe(t) x(t) rΔd,
=αe(t) P(t) (c) Ta, , f
A control system using the coefficient updating algorithm is an echo canceller shown in FIG.

(発明の効果) 以上説明した如く本発明はエコー経路の伝達関数の近似
形を導き、該伝達関数形を生成する回路構成を、RC1
次回路網、乗算器、及び加算器よりなる簡単な構成で実
現したもので、エコーの抑圧効果が大きく、消費電力が
小さく、かつLSI化に適したエコーキャンセラを提供
するものである。
(Effects of the Invention) As explained above, the present invention derives an approximate form of the transfer function of an echo path, and changes the circuit configuration for generating the transfer function form to RC1.
The present invention is realized with a simple configuration consisting of a circuit network, a multiplier, and an adder, and provides an echo canceller that has a large echo suppression effect, low power consumption, and is suitable for LSI implementation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のエコーキャンセラを用いたディノタル加
入者線双方向伝送系のブロック図、第2図は従来の擬似
エコー発生回路、第3図本発明に係るエコーキャンセラ
の回路図である。 1 ・4線側入力端、2・・4線側出力端、3・・・ハ
イブリッド回路A 4°゛擬似工コー発生回路、5・・
・加算器、6・・・加入者線、7、〜7−(N−1)・
・・遅延1 素子、8−0〜8−N ・・乗算器、9・・・加算器、
lo・・・抵抗、11・・・コンデンサ、12.14−
1.14−2゜16 +、 、 16−2 ・・・乗算
器、13・・加算器、15・・・累積加算器、17−1
.17.2 ・・加入者線の終端抵抗。 手続補正書(1−1制 御 事件の表示 昭和58年 特 許 願第154136号2 発明の名
称 エコーキャンセラ 3 補正をする者 事件との関係 特許出願人 任 所(〒105) 東京都港区虎ノ門1丁目7番12
号6 補正の内容 (1) 明細書第4頁第11行目に「17−2はR(Ω
)なる」とあるのを1112は”s(Ω)なる」と補正
する。 (2) 同1−第7頁の(8)式を下記のとおり補正す
る。 (3)同書第9頁第12行目に の全 する。 (4)同書第12頁第8行目に「1回目の」とあるのを
11回の」と補正する。 (5)同書第9頁第12目から第2行目に「Δd1−α
。(t)P(t) (26)式で示される」とあるのを
「Δdにαe(t)P(t)第3図に示すエコーキャン
セラは(26)式で示される」と補正する。 【6ン 同書第13頁第3イテ目〃)も第一4−イテ月
4こ「隼’I御糸力く・−でb る2J と あ る 
− E 「$″1@系 p消1ろもの7ある・青と補正
Tる。
FIG. 1 is a block diagram of a Dinotal subscriber line bidirectional transmission system using a conventional echo canceller, FIG. 2 is a conventional pseudo echo generating circuit, and FIG. 3 is a circuit diagram of an echo canceller according to the present invention. 1. 4-wire side input terminal, 2.. 4-wire side output terminal, 3.. Hybrid circuit A 4° pseudo power cord generation circuit, 5..
・Adder, 6...Subscriber line, 7, ~7-(N-1)・
... Delay 1 element, 8-0 to 8-N ... Multiplier, 9 ... Adder,
lo...Resistance, 11...Capacitor, 12.14-
1.14-2゜16 +, , 16-2... Multiplier, 13... Adder, 15... Cumulative adder, 17-1
.. 17.2 ・Terminal resistance of subscriber line. Written amendment (1-1 control) Display of the case 1982 Patent Application No. 154136 2 Name of the invention Echo Canceller 3 Relationship with the person making the amendment Patent applicant's office (105) Toranomon 1, Minato-ku, Tokyo Chome 7-12
No. 6 Contents of amendment (1) On page 4, line 11 of the specification, “17-2 is R(Ω
) is corrected to 1112 as “s(Ω) becomes”. (2) Formula (8) on page 1-7 of the same is amended as follows. (3) The entire text is on page 9, line 12 of the same book. (4) In the 8th line of page 12 of the same book, the phrase ``1st'' has been amended to read ``11th''. (5) In the second line from page 9, page 9 of the same book, “Δd1−α
. (t)P(t) Expression (26)'' is corrected to read, ``At Δd, αe(t)P(t) The echo canceller shown in FIG. 3 is expressed by Expression (26).'' [6, same book, page 13, 3rd item] also says 1st 4-ite month 4 ``Hayabusa'I Mitorikoku-de bru 2J.''
- E "$"1 @ system p eraser 1 romono 7, blue and correction T.

Claims (1)

【特許請求の範囲】[Claims] エコー経路と擬似エコー経路の信号を相殺するエコーキ
ャンセラにおいて、エコー打消誤差が最小となるよう決
定される2つの係数のうち一方は入力信号と乗算し、他
方はRCI次回路網を介した入力信号と乗算するための
2つの乗算器と、両乗算器の出力を加算する加算器と、
4線側出力へのエコーと前記加算器の出力を相殺する手
段を有することを特徴としたエコーキャンセラ。
In an echo canceller that cancels the signals of the echo path and the pseudo-echo path, one of the two coefficients determined to minimize the echo cancellation error is multiplied by the input signal, and the other is the input signal via the RCI circuit network. two multipliers for multiplying by and an adder for adding the outputs of both multipliers;
An echo canceller comprising means for canceling an echo to a four-wire side output and an output of the adder.
JP15413683A 1983-08-25 1983-08-25 Echo canceller Granted JPS6046625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15413683A JPS6046625A (en) 1983-08-25 1983-08-25 Echo canceller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15413683A JPS6046625A (en) 1983-08-25 1983-08-25 Echo canceller

Publications (2)

Publication Number Publication Date
JPS6046625A true JPS6046625A (en) 1985-03-13
JPS6317371B2 JPS6317371B2 (en) 1988-04-13

Family

ID=15577674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15413683A Granted JPS6046625A (en) 1983-08-25 1983-08-25 Echo canceller

Country Status (1)

Country Link
JP (1) JPS6046625A (en)

Also Published As

Publication number Publication date
JPS6317371B2 (en) 1988-04-13

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