JPS6046048A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the number of custom masks for altering a wiring pattern by forming a contacting hole with a common mask at the predetermined position of a semiconductor device having a multilayer interconnection structure. CONSTITUTION:A lower wiring layer 17 has wirings 17a, 17b, 17c having contactable units 21a-21h, and is formed by a custom photomask formed in a desired pattern. The photomask for forming a contacting hole on an interlayer insulating film 18 is composed in pattern as a common mask for all wiring patterns formed in a row shape, and contacting holes 22a-22i are formed in mere holes 22h even at the position where no lower wiring layer exists. The wirings 23a-23f of an upper wiring layer formed by using the custom photomask are extended to the position where do not cross the holes 22a-22i, and connected through the contacting holes 22e, 22f, 22g, 22i via a contacting wiring unit 28.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same, and in particular to wiring formation of a semiconductor device using a master slice method in which a desired logic is formed by changing the wiring pattern. The present invention relates to a technique that is effective when applied to reduce the number of custom masks in a process and reduce the overall man-hours.

[Background technology]

Various elements are formed on the upper and lower main surfaces of the semiconductor substrate.
, LSI, and other semiconductor devices require wiring to electrically connect each element. With the recent trend toward higher integration and miniaturization of devices, wiring has become multilayered with two or more layers. For example, gate array LSI
Here, a wiring region is provided adjacent to an element formation region called a so-called basic cell, and an interlayer insulating film between two lower wiring layers is formed on this wiring region.

Upper wiring layers are sequentially formed. As a result, a two-layer wiring structure is formed (Japanese Patent Laid-Open No. 57-211
Publication No. 248). A specific example of the process developed by the present inventor to realize such a structure is shown in FIG. Note that in FIG. 1 (AJV-Oi), the interlayer insulating film is omitted for the sake of simplicity. A lower wiring layer (hereinafter referred to as the first aluminum layer) 3 extending in one direction is formed by patterning the aluminum film on 2 by etching.
An interlayer insulating film 4 is formed by depositing an insulating material such as IO, Phos-7 ossilicate glass (PSG), etc. over the entire surface. Next, contact holes 5 are formed by partially etching the interlayer insulating film 4 at required locations.

A part of the first aluminum Ifi3 is exposed through this contact hole 5. By forming an aluminum film thereon and etching it, an upper wiring layer (hereinafter referred to as a second wiring layer) extending over the first aluminum layer is formed.
An aluminum layer) 6 is formed. 1st. A part of each second aluminum layer 3, 6 is electrically connected only in the contact hole 5, and in other parts, the interlayer insulating film 4
As a result, a 2WII wiring structure is obtained which is insulated and separated by .degree.

These first aluminum layers 3. When etching contact hole 5 and second aluminum layer 6, photolithography technology is usually employed. For this reason,
In each step, a process photomask using a negative resist on which a ROM film (or gold film) 43 is formed as shown in FIGS. 2(5) to 2(d) is used. That is, the photomask M1 shown in FIG. 2(5) is used to form the first aluminum layer 3, and the old photomask M4 shown in FIG. 2 is used to form the first aluminum layer 6. Also,
When forming the contact hole 5, the dimensions are usually made slightly different in order to prevent the formation of undesired pinholes caused by foreign matter, and also to prevent short circuits and decreases in breakdown voltage of the line layer described below. Fig. 203), two photomask M of (0), 2. M,3 is used. In other words, a total of four photomasks are used.

By the way, among semiconductor devices, gate array LSI uses a so-called master slicing method in which only elements such as MO8FE and T are formed in advance as a basic design (master), and different wiring is applied according to the user's design specifications. A method is being used to realize a large number of LSIs (products) having various functions. Therefore, it is required to change the patterns of the aluminum layers 3 and 6 of the two-layer wiring structure and the contact holes 5 in accordance with changes in the wiring. For this reason, each time the wiring is changed to manufacture a new product, each photomask M, 1. M2. It is necessary to prepare a photomask whose pattern shape is completely different from that of M3 and M4.

In other words, the photomask is configured as a custom mask dedicated to each wiring pattern, and therefore, each custom mask must be prepared for each different wiring pattern.

Therefore, in the above-mentioned two-layer wiring structure, four custom masks must be prepared depending on the required wiring pattern. As the number of LSI types designed and manufactured using one basic design (mask) increases, that is, as the number of changes in wiring patterns increases, the number of photomasks required becomes enormous. For this reason, it has been found that problems arise in that costs increase and the management and handling of the photomask becomes complicated. In particular, when three or four or more wiring layers are required, the number of customizations becomes extremely large, and the above-mentioned problem turns out to be a fatal drawback when manufacturing semiconductor devices. .

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device in which the number of custom masks for changing wiring patterns is reduced.゛Another object of the present invention is to improve the wiring area by its wiring shape.
It is an object of the present invention to provide a semiconductor device that enables the formation of a semiconductor element of ＼ and achieves high density of the ℃ element, thereby realizing cost reduction and high integration.

Still another object of the present invention is to reduce the number of custom masks required when forming different wiring patterns, thereby reducing costs that depend on the number of custom masks.
A further object of the present invention is to provide a method for manufacturing a semiconductor device that reduces the cost of the semiconductor device and, on the other hand, simplifies the handling of the photomask and improves the B tracking rate.

The above and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings that the present invention is of interest.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a contact hole is set at a position that overlaps one of the upper wiring layer and lower wiring layer, and the other wiring layer is formed so as not to intersect with this contact hole, so that only the area where contact is required is made in the other wiring layer. By extending a part of the wiring layer, any wiring connection can be obtained even if the position of the contact hole is set at a fixed position.
In addition, a custom mask for forming holes is not required, and the number of photomasks is reduced, thereby achieving cost reduction.

In addition, by forming one contact hole in a common mask at a predetermined position, a custom mask can be placed.
By limiting the number of custom masks to only those required for stone formation, the number of custom masks is reduced, their handling and management are simplified, and manufacturing is facilitated and manufacturing efficiency is improved.

[Embodiment 1] FIG. 3 shows an embodiment in which the present invention is applied to a gate array LSI10. A large number of bonding pads 11 are arranged around the rectangular semiconductor chip, and inside the pads 11, output puffers 12 are arranged corresponding to the pads 11. Basic cell areas are arranged in a grid pattern in the center of the chip. The basic cell area is made up of basic cell rows 13 in which a plurality of basic cells 13a are arranged in a row, and further arranged in parallel in a plurality of rows at regular intervals. The basic cell 13a is for forming a desired logic. Normally, the basic cell 13a includes a plurality of semiconductor elements so as to constitute a certain logic, for example, a two-way NAND gate. In this example, there are two P-channel MO8FETs and two N-channel MO8Fs.
0M08 (complementary ffMO8F) configured in combination with ET
ET). Two MOSFETs of the same channel type
The two MOSFETs share semiconductor regions serving as source and drain regions, respectively, and are connected in series.

A wiring region (channel region) 14 is formed between the basic cell rows 13, and wiring is provided for interconnecting the basic cells, people, output buffers 12, and the like. The connection of this wiring can be changed arbitrarily according to the user's request.
In addition, the general wiring has a multilayer wiring structure having two or more wiring layers.

FIG. 4 shows an enlarged view of the arrow A section in FIG. 3. Parts of the basic cell row 13 and wiring area 14 are shown in FIG. Shown in (5).

In addition, in the 4th country, the interlayer insulating film is omitted to simplify the drawing. Below, the 6th and 8th
The same applies to the figures. In the 4th country, each area 13.13a is indicated by a two-dot chain line.

14 are virtually divided.

The basic cell 13a has a gate electrode 4 made of polycrystalline silicon.
1 and an N-channel MO8F'ET formed in a self-aligned manner with the N-channel MO8F'ET, and a P-channel MO8FET (not shown). Has a similar pattern.

It consists of a gate electrode made of polycrystalline silicon and a P" type semiconductor region formed in a self-aligned manner with the gate electrode. When the gate electrode and the semiconductor regions that will become the source and drain regions are completed, this gate array is formed. This is the basic design (mask) of LSI10.

Common to all types of metalwork. In addition, crowd buffer area -1
2 to 2, the basic design is MOSFET in exactly the same way.
ET has been completed. The illustration of the aluminum wiring for the basic cell 13a is omitted.

The wiring area 14 is a basic design (mask) common to all types, and MO8FETQ, Q
It has 2. , MO8F'E'l'QI, Q2 consists of a gate electrode 41 made of polycrystalline silicon and an N+ type semiconductor region 42 formed in a self-aligned manner thereto. Aluminum wiring for TQ+ and Q2 forming the basic cell 13a is not shown. A plurality of MOSFETs provided between each contact hole are arranged in the direction in which the second aluminum layer extends. Figure 4 (in Bl.

The above-mentioned M OS I''ET Q+ and Qt are omitted.

MOS FET Q+ -Qt is provided on the surface of the semiconductor substrate 15 under the insulating film 16.

In the wiring region 14, an insulating film 16 such as a 5ift layer or a PSG film is extended on the main surface of the semiconductor substrate 15, and on this insulating film 16, a lower wiring layer 172, an interlayer insulation ff1ll11B,
Upper arrangement 1J119 and) combination film 20
A two-layer wiring structure is constructed by laminating the following layers in this order. The lower wiring layer 17 is formed as a first aluminum layer. First, an aluminum film is formed on the entire surface by vacuum evaporation method or the like, and then a photoresist film is further formed on the aluminum film by photolithography technology to form a desired pattern. It is formed by exposing a photoresist film using a custom photomask formed in a pattern, developing it, and etching the aluminum film using this as a mask. Here, in this example, the first aluminum layer 17 includes a plurality of interconnections 17 a, 17 b, 17 extending in a continuous or discontinuous manner parallel to the basic cell row 13 (in the lateral direction in the figure).
contactable portions 21a to 21h with increased wiring width are formed on each wiring at equal intervals. Note that the contactable portion can also have the same width as the other portions of the wiring. A photomask M5 for forming the first aluminum layer 17 is shown in FIG. 5(5). This mask is used for exposure using a ℃ contact aligner using a negative resist.

The interlayer insulating film 18 is formed by depositing an insulating material such as Sin or PSG over the entire surface, and then three contact holes are formed thereon by the same photolithography technique. In this case, two photomasks M6 and M7 shown in FIGS. 5(B) and 5(Q) are sequentially used to prevent pinholes and the like from occurring due to foreign matter.

At this time, these photomasks M6. M7 is configured by forming a pattern of contact holes in a matrix and using a common mask for all the wiring patterns in order to accommodate any change in the wiring pattern. Therefore, the contact holes Jv22a to 221 are connected to the contactable parts 22a to 22 of the first aluminum layer 17.
In addition to holes 22h, holes 22h are also formed in areas where the first aluminum layer 17 does not exist.

The masks M6 and M7 are positive resists and are used for exposure with a projection aligner or stepper. This is to prevent cracks from occurring in the interlayer insulating film 18 and the lower wiring 17 due to the presence of foreign matter during pressure bonding, which could cause defects if a negative resist is used and exposed using a contact aligner. For similar reasons,
The mask M8 is also exposed using a projection aligner or stepper using a positive resist. The same applies to the masks shown in FIGS. 7W to 9B and FIGS.

The upper wiring layer 19 is similarly formed using an aluminum film as a second aluminum layer using photolithography technology, and in this example, a plurality of wirings 23a extending in the vertical direction of the figure are perpendicular to the first aluminum layer 17. ~23f. To form this second aluminum layer 19, a custom photomask M8 shown in FIG. 5 is used. What is important here is that each wiring 23a-23f is a contactable portion 21a-21h of the first aluminum layer 17, in other words, a contact hole 22a-22. It intersects with i and extends to a position other than 2. Then, the wiring 2 to be electrically connected to the first aluminum layer 17 in order to obtain the desired logic.
3b, 23d, 23e.

23f corresponds to the first aluminum j@17 wiring 1
Contactable portion 21e of 7b, 17c.

A portion 28 is extended in a protruding manner toward 21f, 21g, and 21h, and contact holes 22el, 22L, 22g, 22
The connection is made through i.

In the figure, the protruding contact wiring portion 28 and the contactable portion have approximately the same shape, but the contactable portion is exaggerated for convenience.

ing.

The passivation film 20 is formed by depositing or coating sio, Si*N4, or polyimide resin on the entire surface to maintain the second aluminum layer 19 and to fill the contact holes 22a, 22, which are partially uncontacted.
b, 22c, 22d.

22h and covering it, the first aluminum layer 1
7 and protects the base.

The gate array LS110 configured as described above has the minimum interval dimension c of the contact holes iy that are allowed to be adjacent to each other and the wiring interval l! of the first aluminum layer 17. However, the dimensions are now 28 μm and 12 μm, respectively, and due to the large number of contact holes formed, the conventional dimensions are 24 μm and 8 μm (
(see Figure 1). Therefore, if the same number of wires as the conventional one is used, the area of the wiring region 14 must be increased, and the chip size will be increased by 30 to 40%.

However, if the spacing of the second aluminum layers is as in this example, it is possible to form a MO8FET element between them. Therefore, as shown in FIG. 4, MO8FETs QI and Ql+ may be formed in the wiring region 14. As a result, the number of gates that can be realized can be nearly doubled compared to the case where only the basic cell region is used, and the increase in chip size can be sufficiently compensated for, and conversely, high integration can be achieved.

Next, let us consider the case where different wirings are formed for the gate array LSI having the above configuration. Figure 6.

(5) is a gate array LSI with different wiring.
Indicates IOA. As in the previous example, the insulating film 1 of the semiconductor substrate 15
A lower wiring layer (first aluminum layer) 17A is formed on 6, an interlayer insulating film 18 is formed thereon, and then an upper wiring layer (second aluminum layer) 19A and a passivation group 20 are formed at .degree. The first aluminum layer 17A is a wiring 24a different from the previous example.

A constitutive formula is obtained from 24b and 24c. These formations include the seventh
A custom σ) photomask M9 for negative resist shown in FIG. 5 is used. Similarly, contactable portions 258 to 25g are formed in each wiring of this first aluminum layer 17A. Its position is the contactable part 21a in FIG.
It is arranged so that it overlaps with 21h. To form contact holes in the interlayer insulating film 18, the seventh
As shown in Figures (B) and (0), use the same positive resist photomasks M6 and M7 as in Figure 5 (Bl, (01). With this, a new custom mask is prepared for forming the contact hole. It is not necessary, all wiring] (just prepare two common masks that match the turns. With these photomasks M6 and M7, a simple hole 26e
.

Contact holes 26a to 26i including 26 holes are the first
Contactable portions 258-25 of aluminum layer 17A
g and other parts.

Next, the second aluminum layer 19A forms wiring lines 27a to 27f using a custom photomask MIO for positive resist shown in FIG. part 2 of the area where electrical connection is required.
9 to contact holes 26a, 26d, 26f, 26i
It extends in a convex shape towards.

In this way, at least when forming contact holes, a custom mask is not required and the same mask can be used regardless of the difference in wiring pattern. This allows you to change the custom mask due to wiring changes in the first step. This means that two photomasks for the second aluminum layer are sufficient. Therefore, the number of custom masks can be halved from the conventional four to two, reducing the manufacturing cost of custom masks and simplifying their management and handling. In particular, when pattern exposure of contact holes is performed, manufacturing efficiency can be improved without the need to replace the photomask in the exposure device, and together with the above-mentioned cost reduction of the photomask, product cost can be reduced.

[Embodiment 2] FIG. 8 shows another embodiment of the device of the present invention, and particularly shows only the wiring structure formed in the wiring area.

In the figure, 30 is the lower wiring layer (first aluminum layer), and 31 is the upper wiring layer (second aluminum layer) formed on the first aluminum layer 3o via an interlayer insulating film (not shown). ). The first aluminum layer 30 is made of a custom photomask M for negative resist shown in FIG. 9(5).
For example, four lines 32a to 32d are extended in a straight line parallel to the basic cell region (in the lateral direction in the figure) using 11, and a plurality of contactable parts 34 are formed in the middle. In this case, in this example, the contactable portions of adjacent wirings are formed so as to be shifted by half a pitch in the extending direction, or to be located at mutually opposite positions. In this example, the wiring spacing is l.

12μm, minimum distance (pitch) of contactable parts 2
+ is 12 μm.

The contact holes formed in the glabella insulating film 33 are formed using a positive resist photomask M12. as shown in ) and ρ) in FIG.
A contact hole 35 is formed on all of the contactable portions 34 of the first aluminum plate 30 using M13. In order to make the pitch of the wiring finer, the contact holes are formed at an angle of about 45 degrees compared to normal ones. In this case as well, the photomask Ml 2. Ml 3 is configured as a mask common to all types in which contact hole patterns are regularly arranged.

The second aluminum layer 31 is formed using a custom photomask M14 for positive resist like a spade in FIG. In this case as well, each wiring in the second aluminum layer 31 is formed so as not to intersect with the contact hole 35, and a part of the wiring 37 is extended in a convex shape toward the contact hole only in the area where connection is required. We are trying to establish a connection.

In the above wiring structure, it is not necessary to increase the interval between each wiring so much as compared to the conventional one, and the chip size can be formed to be approximately the same as that of the conventional one. However, it is not possible to form elements in the wiring area as in the previous example.

On the other hand, also in this example, the first. 2nd aluminum N30
, 31, any wiring can be obtained by simply changing the photomasks, and the same photomasks can be used for forming contact holes.

Therefore, as in the previous example, it is possible to reduce the number of custom masks, simplify the management and handling of the masks, and improve manufacturing efficiency and reduce costs.

〔effect〕

(1) In a multilayer wiring structure in which the upper and lower wiring layers are formed with an interlayer insulating layer in between, and both layers are connected through a contact hole formed in the interlayer insulating film, one of the wiring layers is the contact hole. In addition to placing it in the same position as the layer,
The other wiring layer is extended so as not to intersect with this contact hole, and a part of it is extended only in the places where contact is required, so that the contact hole can be placed at a fixed position regardless of the difference in wiring. There is no need to use a dedicated (custom) mask with a different pattern shape for each different wiring.

(2) In the upper and lower wiring layer structure, a custom mask is used when forming each wiring layer, and a mask with the same pattern can be used for all wiring when forming contact holes. In this case, the number of custom masks can be reduced from the conventional 04 to 2, and the number of custom masks can be halved.

(3) It is only necessary to prepare a custom mask for forming wiring layers, and no custom mask is required for forming contact poles. This reduces the number of custom masks, simplifies their management and handling, and reduces costs. It is possible to reduce the At the same time, since there is no need to replace the photomask each time a contact hole is formed, it is possible to reduce the number of manufacturing steps, improve manufacturing efficiency, and reduce product costs.

(4) Since the contact hole position can be set at a constant location regardless of the difference in wiring, it is possible to form semiconductor elements within the wiring area, and high density and high integration of semiconductor elements can be achieved.

(5) If the difference in wiring is slight, wiring can be done by simply changing the pattern on either the lower or upper wiring layer. In this case, only one custom mask is needed to customize the wiring. The number of masks can be further reduced and the manufacturing process can be shortened.

(6) By arranging the contact holes so that they are shifted by half a pitch while the other wiring layer has a shape close to a zigzag, the spacing between the wiring layers can be kept at the same level as before, and the chip size can be avoided. do not have.

Although the invention which has been thoroughly enjoyed by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is. For example, the patterns of each wiring layer and the patterns of contact holes are not limited to those of the embodiments described above. Also, instead of the custom photomask MIO shown in Fig. 5, the photomask shown in Fig. 10 is used. A similar function can be obtained by using a photomask M15 having a pattern. When photomask 15 is used, a second aluminum layer is formed over all contact holes including simple holes. Therefore, when a custom photomask M15 is used, wiring can be completed by simply connecting the second aluminum layer above the (contact) hole and the upper wiring layer extending in the vertical direction in the figure at a desired position using the connecting portion 40. be completed. This is advantageous for changing the logic by using a single custom photomask containing only M2S in a plurality of products with slight differences in wiring patterns. Furthermore, the present invention can be similarly applied to a multilayer wiring structure having three or more wiring layers.

Further, the wiring layer may not be made of a metal material such as aluminum (but may be any wiring layer such as a polysilicon wiring layer).The upper and lower wiring layers of each of the above embodiments are It is also possible to configure the structure so that the relationship is reversed.In other words, the lower wiring layer is formed using photomask M8 or MIO, the holes are formed using photomasks M6 and M7, and then photomask M5 or M9 is formed. The same applies to Example 2. Even in this case, the same effect as in the above-mentioned example can be obtained. In this case as well, M2S may be used in place of the photomask M8. .

[Application field]

The above explanation will mainly focus on the field of application of the invention made by the present inventor, which is the gate array LSI.
Although we have explained the case where it is applied to a master slice type semiconductor device or any other semiconductor device that has a multilayer wiring structure, it is not limited to gate array LSI, but can be applied to all semiconductor devices. I can do it.

(5) is a cross-sectional view taken along the BB line at the fourth time, Figure 2 (5) to flat are plane pattern diagrams of the photomasks used, Figure 3 is a plane view of the gate array to which the present invention is applied, and Figure 4 is the third This is an enlarged view of a part of the figure (part A), where the figure is a plan view, (Bl is a cross-sectional view taken along the line BB in figure (5), and figures 5 to 5).
is a plane pattern diagram of the photomask used, and Figure 6 shows the state in which the wiring is different. (5), (B)
are the 41st prisoner, the plan view and cross-sectional view corresponding to @, and #! 7
Fig. 8 is a plan view of the main parts of another embodiment; Figs. 9-I are plan pattern views of the photomask used; Fig. 10 is a plan view of the photomask FIG.

10... Gate array LSI, 13... Basic cell row, 13a... Basic cell, 14... Wiring area, 17.
17A...first aluminum layer (lower wiring R), 17
a to 17c... Wiring, 18... Interlayer insulating film, 19.
. . . second aluminum layer (upper wiring layer), 20 . . . passivation film, 21a to 21h . . . contactable portion.

22a-22i...contact hole, 23a-23
f...Wiring, 24 a-24 c...Wiring, 2
58~25g...Contactable part, 26a~26i
...Contact hole, 27a-27f...Wiring,
28° 29... Extension portion, 30... First aluminum layer, 31... Second aluminum layer, 32a to 32d.
... Wiring, 34... Contactable part, 35... Contact hole y, 36 a to 36 e... - Wiring, 37
...Extension part 5M5゜M8. M9. Ml O, Ml 1
．． Ml 3...Custom mask, M6. M7. Ml
2. Ml 3...Mask.

Figure 5 (A) Di3 (6) 4, / Figure 5 (C) (D) ,z,,7' Figure 6 (A) (B) Figure 7 (IV) (B) Figure 7 (C) (D) J Figure 8 ,,? / No. 9 4. j (c) (D)

Claims (1)

[Claims] 1. In a semiconductor device having a multilayer wiring structure of two or more layers in which a lower wiring layer and an upper wiring layer are formed with an interlayer insulating film sandwiched therebetween, the interlayer insulating film includes a layer that overlaps one of the wiring layers. A semiconductor device characterized in that a contact hole is formed at a position that does not overlap with another wiring layer, and a part of the contact hole of the other wiring layer is extended to the hole position as necessary. 2. The lower wiring layer and the lower wiring layer are spaced apart from each other in a substantially perpendicular direction, and the contact hole is formed at a position overlapping the lower wiring layer and facing the upper wiring layer. 1. Semiconductor device described in Section 1. 3. A semiconductor device according to claim 2, wherein an element is arranged in a wiring region between contact holes. 4. A plurality of contact holes are arranged side by side, and are arranged in parallel to each other in the direction of extension at positions overlapping one of the wiring layers, and the other wiring layer is formed in a zigzag shape to avoid each contact hole. A semiconductor device according to claim 1. 5. The semiconductor device according to any one of claims 1 to 4, which is a gate array having a basic cell region in which elements are formed and a wiring region forming a multilayer wiring structure. 6. Form a lower wiring layer using a custom mask formed in a desired pattern, form contact holes in the interlayer insulating film using a mask formed in a certain pattern,
1. A method of manufacturing a semiconductor device, comprising: then forming an upper wiring layer using a custom mask formed into a desired pattern to form a multilayer wiring structure. 7. After forming an aluminum layer on the entire surface, etching the first aluminum layer using a custom mask.
A contact hole is formed using a mask in the interlayer insulating film at a position overlapping the wiring of the aluminum layer, and the aluminum layer formed on the entire surface is pattern-etched using a custom mask to form a second aluminum layer. A method for manufacturing a semiconductor device according to claim 6. 8. The semiconductor device according to claim 7, wherein the custom masks of the first aluminum layer and the second aluminum layer are changed by -J'%F, and the wiring is changed using the contact hole mask as it is. Production method.