JPH0122734B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master slice integrated circuit device that is easy to layout.

In recent years, master slice type integrated circuit devices have been increasingly used in communication devices, computers, and the like. A master slice type integrated circuit device is realized by regularly arranging several transistors and forming a conductive film pattern on a regular grid. Therefore, the design period is short and the development cost is low.

There are two types of master slice type integrated circuit devices: one with two layers of aluminum (Al) conductive film pattern and the other with one layer. Although the two-layer type has the advantage of having a high degree of freedom, a small chip area, and good characteristics, it has the disadvantage that three masks are required, which increases the cost compared to one mask of the single-layer type.

FIG. 1 is a plan view of an example of a basic cell of a conventional single-layer master slice.

A p-well 2 is provided in an n-type silicon substrate 1, and an n ⁺ source/drain region 4 is provided within the p-well 2.
The portion 12b sandwiched between regions 4 is an n-channel. A p ⁺ source/drain region 3 and a p channel 12a are provided in other parts of the substrate 1. These element regions are covered with a thin gate oxide film, the other parts are covered with a thick field oxide film, and gate electrodes 8a, 8b and field through line 8c are provided with a polysilicon film. As a result, a p-channel MOS transistor and an n-channel MOS transistor are obtained. In addition, there are contact holes 9a and 9b for each source/drain layer, an N ⁺ layer 5 for applying substrate voltage and its contact hole 9c, and an Al conductive film 11 for the V _DD line.
a. A p+ layer 6 for applying a p-well voltage and its contact hole 9d, an Al conductive film 11b for a V _SS line, and a contact hole 9a to the polysilicon layer are provided. This yields the basic cell of the master slice.

The functional circuit is formed by an Al conductive film pattern on the y grid 10a shown by the broken line and the x grid 10b shown by the broken line, and the Al conductive film pattern includes an Al conductive film 11a for the _VDD line and an Al conductive film for the _VSS line 11a, a group of source/rain region contact holes 9b, and a group of contact holes 9a on the polysilicon layer.

In this case, the problem is how to arrange the contact holes 9a so that the Al conductive film pattern passing through the y-lattice 10a can be connected without intersecting any positional relationship of the wirings. Conventionally, y grid 1
Although the contact hole 9a is arranged at a position shifted from 0a, it took a lot of time to consider this arrangement. In this case, the layout becomes complicated and the overall area increases, and the wiring design is difficult due to the complicated layout, leading to errors.

FIGS. 2a and 2b are circuit diagrams of examples of functional circuits formed using master slices.

Although the functional circuit shown in FIG. 2a can be easily created using the basic cell shown in FIG. 1, the functional circuit shown in FIG. 2b cannot be realized. In the circuit of FIG. 2b, three input terminals A, φ _A , and φ _B are required. However, since the conventional basic cell shown in FIG. 1 has only two contact holes 8a and 8b that serve as input points, the circuit shown in FIG. 2b cannot be realized with the basic cell shown in FIG.

As described above, the conventional master slice basic cell has the disadvantage that the wiring layout is complicated and difficult to design, and that it cannot be realized depending on the type of functional circuit.

The present invention eliminates the above-mentioned drawbacks, and provides a master slice type integrated circuit device that increases the degree of freedom in wiring the arrangement positions of contact holes, maintains regularity, and facilitates arrangement.

The integrated circuit device of the present invention includes a plurality of circuits connected in series by source and drain regions on a silicon substrate.
A MOS transistor, an input gate wiring layer provided for each MOS transistor on the silicon substrate via an insulating film, and a conductive wiring connecting each of the source/drain regions and the input gate wiring layer. In the integrated circuit device, the input gate wiring layer has at least three contact forming portions including both ends, and adjacent contacts of the at least three contact forming portions of the one input gate wiring layer Each of the first contact forming part and the second contact forming part forms the first contact forming part and the second contact forming part of each input gate wiring layer adjacent to the left and right sides of the one input gate wiring layer. At least two conductive wires are disposed on a straight line passing through each of the contact forming parts and parallel to the straight line passing through the contact forming part between the contact forming part and the first contact forming part.

Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a plan view of one embodiment of the present invention.

Providing a p well 2, a p ⁺ source/drain region 3, an n ⁺ source/drain region 4, an n ⁺ layer 5 for voltage application, and a p ⁺ layer 6 in the semiconductor substrate 1 is the same as in the conventional case. The difference from the conventional one is the polysilicon layer 8.
Contact holes formed in d to 8j, e.g. 9
h ₁ , 9h ₂ are formed on the y grids 10a ₁ , 10a ₄ ,
Two y-grids 10a ₂ and 10a ₃ are provided in the middle. Here, polysilicon 8d and 8f are input gate electrodes of a p ^- channel MOS transistor (hereinafter referred to as p-MOST) having a p + source/drain region 3, and polysilicon 8h and 8j are n input gate electrodes having an n ⁺ source/drain region 4. When the input gate electrode of the channel MOS transistor (hereinafter referred to as n-MOST) and the y-lattice 10a ₀ are the boundaries of the basic cell,
Channel changing polysilicon layers 8e, 8i for avoiding intersection with the Al conductive film pattern on the y-lattice 10a ₀
The feed through wire is 8g. The contact 9b of the P ⁺ source/drain region is the y-lattice 10a ₆ , 10
At least one y-grid 10a ₅ or 10a ₁₀ is provided on a ₉ and between the polysilicon layer contact holes 9h ₄ or 9h ₅ . Polysilicon layers 8d to 8j
The upper contact hole is symmetrical about the center line X-X' with respect to the coordinates represented by the x and y grid,
Polysilicon layer 8d for input gate of p-MOST,
8f has a contact hole _9h5 on the y-lattice _10a11 , and is not connected to the input gate polysilicon layers 8h and 8j of the n-MOST. The channel changing polysilicon layer 8e is between the input gate polysilicon layers 8d and 8f, and there is an x-lattice _10b5 having no polysilicon.

The arrangement of the basic cells is as follows: on the left and right of the basic cell in Fig. 3, the x lattice 10b ₆ of the basic cell in Fig. ₃ is located at the position of x lattice 10b 0, and the basic cell of Fig. 3 is located at the position of x lattice 10b ₇ . The x-lattice 10b ₁ is arranged in such a manner that the basic cells of FIG. 3 move in parallel, and a plurality of similar cells are arranged in the horizontal direction. Also, the horizontal arrangement of these plural cells is such that the y-lattice 10a _{0 '} of the basic cell in FIG. 3 is at the position of the y-lattice 10a ₀ in FIG. A y-lattice 10a ₀ of basic cells in FIG. 3 is arranged.

In the above arrangement, the x-lattice 10b ₀ of FIG.
10b ₇ , x-lattice 10a ₀ , 10a ₀ ' may be arranged so as to be line symmetrical with respect to each other.

In FIG. 3, connections with the polysilicon layer are made through contact holes _9h1 , _9h4, etc. on the y-lattice _10a0 to 10a.
Any Al conductive film pattern can be formed on 0a ₅ , 10a ₁₀ to 10a ₁₂ .

FIG. 4 is a plan view of an example in which the y-lattice of the embodiment shown in FIG. 3 is changed.

A y-lattice 10c 2 is formed between the contact hole rows 10c ₁ and 10c ₅ on the polysilicon layers 8d to 8j in FIG _.
~10c ₄ , 10c 6 , ₁₀ between contact hole row 10c ₈ and hole row 10c ₅ of source/drain region 3
A plurality of y gratings may be provided above c ₇ and 10c ₁ instead of 10a ₀ in FIG. 3.

FIG. 5 is a plan view of another example in which the y-lattice of the embodiment shown in FIG. 3 is changed.

Y grid 10 of contact holes in polysilicon layer
c ₂ , 10c ₅ , 10c ₈ , and further 10c ₉ , 1
It may be formed on _0c12 . It is not limited to this, and the same shape may be added above or below. Furthermore,
Regardless of the line of symmetry
- That of the MOST part (lower part of X-X' in Figure 3)
may be formed by a combination of FIGS. 3, 4, and 5. Also, instead of two MOSTs connected in series in FIG. 3, three or more MOSTs may be connected in series.

As explained in detail above, according to the present invention, the degree of freedom in wiring is high and the pattern is regular, so that it is possible to obtain a master slice type integrated circuit device that is easy to design and has fewer wiring errors. is big.

[Brief explanation of drawings]

FIG. 1 is a plan view of an example of a basic cell of a conventional single-layer master slice, FIGS. 2a and b are circuit diagrams of an example of a functional circuit formed using the master slice, and FIG. Plan view of one embodiment of 4th
This figure is a plan view of a modified example of the Y grid of the embodiment shown in FIG. 3, and FIG. 5 is a plan view of another modified example of the Y grid of the embodiment shown in FIG. 1...n type silicon substrate, 2...p well, 3...
p ⁺ source/drain region, 4...n ⁺ source/drain region, 5...n ⁺ layer, 6...p ⁺ layer, 8a-8b...
Gate electrode, 8c...Feed through line, 8d~8
j...Polysilicon layer, 9a to 9d, _9h1 to _9h5 ...
Contact hole, 10a, 10a ₀ to 10a ₁₂ ...y lattice, 10b, 10b ₁ to 10b ₆ ...x lattice, 10c ₁ to
10c ₁₂ ...Contact hole row, 11a, 11b...Al
conductive film.

Claims (1)

[Claims] 1. Multiple MOS transistors connected in series by source/drain regions on a silicon substrate,
An integrated circuit device having an input gate wiring layer provided for each MOS transistor on the silicon substrate via an insulating film, and conductive wiring connecting each of the source/drain regions and the input gate wiring layer. , the input gate wiring layer has at least three contact forming portions including both ends, and adjacent first contact forming portions of the at least three contact forming portions of the one input gate wiring layer and the second contact forming portion respectively correspond to the first contact forming portion and the second contact forming portion of each input gate wiring layer adjacent to the left and right sides of the one input gate wiring layer. An integrated circuit device, comprising at least two conductive wires that are on a straight line passing through the first contact forming part and parallel to the straight line passing through the first contact forming part.