JPS6046033A - Manufacture of dielectric insulator isolating substrate - Google Patents

Manufacture of dielectric insulator isolating substrate

Info

Publication number
JPS6046033A
JPS6046033A JP15386183A JP15386183A JPS6046033A JP S6046033 A JPS6046033 A JP S6046033A JP 15386183 A JP15386183 A JP 15386183A JP 15386183 A JP15386183 A JP 15386183A JP S6046033 A JPS6046033 A JP S6046033A
Authority
JP
Japan
Prior art keywords
corner
etching
size
etching solution
groove width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15386183A
Other languages
Japanese (ja)
Other versions
JPH0154855B2 (en
Inventor
Masahide Miwa
三輪 正英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15386183A priority Critical patent/JPS6046033A/en
Publication of JPS6046033A publication Critical patent/JPS6046033A/en
Publication of JPH0154855B2 publication Critical patent/JPH0154855B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To minimize the size and to increase the density of an isolated dielectric insulator island by expressing the relationship between the size of a corner compensating pattern and the isolating V-shaped groove width or etching depth for preventing the under cutting of the corner of the isolated insulator island in a specific relation formula. CONSTITUTION:Aqueous alkali solution as an anisotropic etchant of a single crystal silicon substrate with a crystalline surface 100 as a main surface has hydroxided potassium, pure water and isopropyl alcohol, and 15% or more of volume rate of isopropyl alcohol is added to aqueous hydroxided potassium solution having 20% or more of weight concentration of the hydroxided potassium. The size (l) of the corner compensating pattern formed at the outside corner of the etching mask of the isolated insulator island can be expressed by l=aw+b or l=ah+b in the relationship to the isolated V-shaped groove width W or the etching depth h. For example, (a) is 0.4-0.5, (b) is -9--4, and the compensating pattern satisfies l=aw+b of the correlation formula in a range of 0.4W-9<=l<=0.5W-4.

Description

【発明の詳細な説明】 (1)発明の属する技術分野の説明 本発明は半導体集積回路、特にモノリシック半導体集積
回路に用いられる絶縁分離基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a method for manufacturing an insulating isolation substrate used in a semiconductor integrated circuit, particularly a monolithic semiconductor integrated circuit.

(2)従来技術の説明 誘電体絶縁分離形の半導体集積回路装置では多数の回路
構成素子(トランジスター、ダイオード、サイリスター
、抵抗、容量等)は誘電体絶縁物分離島(以下絶縁分離
島と称す)内に形成され、各回路構成素子の電気的特性
は絶縁分離島の形状寸法に影響される。
(2) Description of the prior art In a dielectric isolation type semiconductor integrated circuit device, many circuit components (transistors, diodes, thyristors, resistors, capacitors, etc.) are dielectric isolation islands (hereinafter referred to as isolation islands). The electrical characteristics of each circuit component are influenced by the geometry of the isolation island.

第1図は従来の誘電体絶縁分離法による半導体集積回路
の部分断面楔形図であって、第2図によシ絶縁分離島の
製作方法を説明すると第2図(a)に示す単結晶シリコ
ン基板lで通常結晶方位(100)面を主面として結晶
面方位によってエツチング速度の差を有するアルカリ系
のエツチング液による異方性エツチング技術によシ複数
の分離1字溝2を形成し、形成した分離1字溝に誘電体
絶縁分離膜3、例えば二酸化シリコン膜を形成し、さら
にその上に気相成長反応等によシ支持体層4として多結
晶シリコン層を成長させ、しかる後に多結晶シリコンの
支持体層を研磨等の方法によシ研磨面5まで平担にし次
にこの研磨面5を基準面として単結晶シリコン側を研磨
面5′まで研磨することによシ絶縁分離島6を所定の深
さに形成する。従来結晶面(100)を主面とする単結
晶シリコン基板にアルカリ系水溶液による異方性エツチ
ングで耐腐食性エツチングマスク、例えば二酸化シリコ
ン膜を用いて結晶面(111)を有する分離1字溝を設
ける場合、第3図に示す如く各絶縁分離島の底面部に相
当するエツチングマスク8の外側隅角部8aでは結晶面
(100)と結晶面(111)との中間的なエツチング
速度を有する他の面、使用するアルカリ系エツチング液
の組成によって異なるが、例えば(110)面、(21
1)面、(331)面等が出現し、エツチングマスクの
下側にもエツチングが進行するアンダーカッテングが生
じ絶縁分離島の外側隅角部を丸くし絶縁分離島の形状寸
法を設計値よりも小さくし該絶縁分離島内に構築する各
回路素子の電気的特性を悪くする。とのアンダーカッテ
ングを防止するため第4図に示されるようなエツチング
マスク8の外側隅角部に補償パターン9t一つけて補償
することが特公昭45−17988号公報で開示されて
いる。この特公昭45−17988号公報によれば第4
図に示す角部補償パターンを付けて隅角部を補償するた
めの角部補償パターン9の一辺の長さ!紘分離V字溝幅
Wとまたげ該分離7字溝幅からh * W/1an54
.7°で一義的に決まるエツチング探さhと次の相関式
を満足しなけれにならない。
FIG. 1 is a partial wedge-shaped cross-sectional view of a semiconductor integrated circuit formed by a conventional dielectric isolation method. A plurality of separated single-shaped grooves 2 are formed on a substrate 1 using an anisotropic etching technique using an alkaline etching solution that has a difference in etching speed depending on the crystal plane orientation, with the (100) plane as the main plane. A dielectric insulating separation film 3, for example, a silicon dioxide film, is formed in the separated single-shaped groove, and a polycrystalline silicon layer is grown thereon as a support layer 4 by a vapor phase growth reaction. The silicon support layer is flattened to the polished surface 5 by a method such as polishing, and then the monocrystalline silicon side is polished to the polished surface 5' using this polished surface 5 as a reference surface, thereby forming the insulating isolation islands 6. is formed to a predetermined depth. Conventionally, a single-crystal silicon substrate with a crystal plane (100) as its main surface is anisotropically etched with an alkaline aqueous solution to form a single-character separation groove with a crystal plane (111) using a corrosion-resistant etching mask, such as a silicon dioxide film. When provided, as shown in FIG. 3, the outer corner portion 8a of the etching mask 8 corresponding to the bottom surface of each insulation isolation island has an etching rate intermediate between that of the crystal plane (100) and the crystal plane (111). Although the plane differs depending on the composition of the alkaline etching solution used, for example, (110) plane, (21
1) planes, (331) planes, etc. appear, and undercutting occurs where etching progresses under the etching mask. The outer corner of the isolation island is rounded, and the shape and dimensions of the isolation island are made smaller than the design values. This reduces the electrical characteristics of each circuit element built within the isolation island. In order to prevent undercutting, Japanese Patent Publication No. 17988/1988 discloses that a compensation pattern 9t is provided at the outer corner of the etching mask 8 as shown in FIG. 4 to compensate. According to this Japanese Patent Publication No. 45-17988, the fourth
The length of one side of the corner compensation pattern 9 for compensating the corner with the corner compensation pattern shown in the figure! h *W/1an54 from the width of the isolation V-shaped groove W and the width of the separation 7-shaped groove
.. The etching search h, which is uniquely determined by 7°, must satisfy the following correlation formula.

!=Kh 又はi≧KW/lan 54.7° −・・
−・・−+1)ここでKはアルカリ系エツチング液とし
て水酸化論理(KOI()、純水(H,0)、。−プ。
! =Kh or i≧KW/lan 54.7° −・・
-...-+1) Here, K is a hydroxide logic (KOI(), pure water (H, 0), .-p) as an alkaline etching solution.

パノール(C)lsCHtCH*OH)を組成とするエ
ツチング液の結晶面(100)に対する結晶面(110
)のエツチング速度比でアシ、代表釣力組成KOH:1
5g、H*0:50mノ、CHsOHtCHvOH: 
15mi”t’はKの値は約3/10至乃4/lOとな
る。上記の関係式(1)による角部補償を行々う場合に
は同時に第5図のハクテングで示した範囲での隣接する
絶縁分離島のエツチングマスクの相互干渉を紡ぐエツチ
ングマスク禁止領域10が必要である。
The crystal plane (110
) with etching speed ratio of reeds, representative fishing force composition KOH: 1
5g, H*0: 50m, CHsOHtCHvOH:
For 15mi"t', the value of K is about 3/10 to 4/lO. When performing corner compensation using the above relational expression (1), at the same time An etching mask prohibited area 10 is required to avoid mutual interference of etching masks of adjacent insulation isolation islands.

誘電体絶縁分離基板は通常の単結晶シリコン基板に比し
て第2図での製造方法で述べた如く多数の製造プロセス
が必要となるため製造コストが高く該基板上に半導体集
積回路を構築する場合にはベレット寸法を最小化する必
要がおる。
Compared to a normal single-crystal silicon substrate, a dielectric insulating isolation substrate requires a large number of manufacturing processes as described in the manufacturing method shown in FIG. In some cases, it is necessary to minimize the pellet dimensions.

ベレット寸法を最小イ2ヒするには半導体集積回路の各
構成素子が電気的特性上から必要となる最小限の大きさ
の絶縁分離島を高密度に形成しなければならない。高密
度化にさいしては絶縁分離島の外形寸法特に絶縁分離島
の深さは分離7字溝幅によって決まシ、さらには第2図
の誘′亀体分離基板の製造プロセス内での第2図(C)
の研磨による研磨式を見込んだエツチング深さによって
一義的に最小分離7字溝幅が決まシさらに該分@V字溝
幅に対して(11式から角部補償パターンの寸法が決ま
る。
In order to minimize the bullet size, it is necessary to form insulating isolation islands of the minimum size necessary for each component of the semiconductor integrated circuit in view of the electrical characteristics at a high density. In order to increase the density, the external dimensions of the insulation isolation island, especially the depth of the insulation isolation island, are determined by the width of the isolation groove, and furthermore, the Diagram (C)
The minimum separation 7-shaped groove width is uniquely determined by the etching depth taking into account the polishing method by polishing.Furthermore, the dimensions of the corner compensation pattern are determined by the corresponding @V-shaped groove width (from equation 11).

しかしながら(1)式による角部補償パターンの寸法を
取る場合には他の隣接するエツチングマスク間に禁止領
域が必要でおる為最小な分離7字溝幅では分離7字溝幅
が狭すぎたシまた絶縁分離島の最小可能な大きさが制限
されたシまた分離7字溝幅WがW)Oの乗件下では常に
角部補償が必要となシ絶縁分離島の高密度化及びベレッ
ト寸法の最小化を妨げ誘電体絶縁分離基板を使用する半
導体集積回路の価格をあげるという欠点があった。
However, when taking the dimensions of the corner compensation pattern according to equation (1), a prohibited area is required between other adjacent etching masks, so the minimum width of the 7-shaped separation groove is used for a pattern where the width of the 7-shaped separation groove is too narrow. In addition, the minimum possible size of the insulation isolation island is limited, and corner compensation is always required under the condition that the isolation groove width W is W)O. This has the disadvantage that it hinders the minimization of the dielectric insulation and increases the cost of semiconductor integrated circuits using dielectric isolation substrates.

(3)発明の詳細な説明 本発明は絶縁分離島の隅角部のアンターカッテングを防
止する為の角部補償パターンに関して、アルカリ系エツ
チング液の組成及びエツチング液濃度及びエツチング液
温度に関するエツチング条件の最適化を行ない角部補償
パターンの寸法ノと分離v字溝Il@W又はエツチング
深さhとの関係を、 !=ah−)−b又は!−aw−1−b ・・・・・・
・・・(2)なる関係式で表わすことができるようにし
て上記欠点を解決し誘電体絶縁分離島最小化及び高密度
化を可能にする誘電体絶縁分離基板の製造方法を提供す
ることにある。
(3) Detailed Description of the Invention The present invention relates to corner compensation patterns for preventing undercutting of the corners of insulation isolation islands by adjusting etching conditions regarding the composition of an alkaline etching solution, etching solution concentration, and etching solution temperature. After optimization, the relationship between the dimensions of the corner compensation pattern and the separation V-shaped groove Il@W or the etching depth h is determined as follows. =ah-)-b or! -aw-1-b ・・・・・・
To provide a method for manufacturing a dielectric isolation substrate that can be expressed by the relational expression (2), solves the above drawbacks, and makes it possible to minimize dielectric isolation islands and increase density. be.

(4)発明の構成 本発明は、結晶面(100)を主面とする単結晶シリコ
ン基板の異方性エツチング液とじてのアルカリ系水溶液
として水酸化純理、純水、イソプロピルアルコールから
なる組成とし水酸化純理の重量濃度が20チ以上である
水酸化加珪水溶液にインプロピルアルコールを容量比率
15チ以上添加するエツチング液構成と、該エツチング
液に対して絶縁分離島のエツチングマスクの外側隅角部
に設ける角部補償ノ(ターンの大きさく至)を分離V字
溝幅(W)又はエツチング深さ中)との関係においてA
=aW+El又はp=ah−1−bで表わすことができ
るようにし該相関式においてaは0.4乃至0.5.b
は−9乃至−4なる値を取シ角部補償パターンはo、 
4w−9≦ノ≦0.5W−4の範囲内での相関式ノーa
 w −) bを満足させる方法によシ構成する。
(4) Structure of the Invention The present invention uses a composition consisting of pure hydroxide, pure water, and isopropyl alcohol as an alkaline aqueous solution as an anisotropic etching solution for a single crystal silicon substrate having a crystal plane (100) as its main surface. An etching solution composition in which inpropyl alcohol is added at a volume ratio of 15 or more to a silicon hydroxide aqueous solution with a weight concentration of 20 or more, and an outer corner of an etching mask of an insulating isolation island with respect to the etching solution. A in relation to the corner compensation hole (turn size) provided in the section with the separation V-groove width (W) or etching depth).
=aW+El or p=ah-1-b, and in this correlation equation, a is 0.4 to 0.5. b
takes a value between -9 and -4, and the corner compensation pattern is o,
Correlation formula no a within the range of 4w-9≦no≦0.5W-4
w −) Construct in a way that satisfies b.

(5)実施例の説明 次に本発明の詳細な説明する。(5) Description of examples Next, the present invention will be explained in detail.

本発明におけるアルカリ系エツチング液としては水酸化
純理(KOH)、純水(ush) 、インプロピルアル
コール((OH,)、CHOH)を組 )成とするエツ
チング液を使用する。単結晶シリコン基板の結晶面(1
00)のエツチング速度はエツチング液の濃度と温度に
依存する。本発明におけるアルカリ系エツチング液では
エツチング速度とエツチング液温度紘第6図に示すよう
な単調増加の関係にアシ、液温80℃でエツチング速度
はほぼ1μm/分である。一方エッチング液の水酸化加
珪重量濃度とエツチング速度については第7図に示すよ
うな関係を有することが実験結果から判った。第7図よ
シ水酸化論理重量濃度35%の時エツチング速度は最大
となシ水酸化論理重量濃度20チ以上であればエツチン
グ速度として0.8μm/分以上の高い速度を得られる
ことが判る。絶縁分離島の隅角部のアンダーカッテング
についてはアンダーカッテング抑止剤として水酸化加珪
水溶液に添加するインプロピルアルコールの容量濃度と
の間に第8図に示すような関係があ夛イソプロピルアル
コールの添加濃度が15チ以上であればアンダーカッテ
ングが少々くなる結果を得た。
As the alkaline etching solution in the present invention, an etching solution composed of pure hydroxide (KOH), pure water (ush), and inpropyl alcohol ((OH, ), CHOH) is used. Crystal plane of single crystal silicon substrate (1
The etching rate of 00) depends on the concentration and temperature of the etching solution. The alkaline etching solution used in the present invention has a monotonically increasing relationship between the etching rate and the etching solution temperature as shown in FIG. 6, and the etching rate is approximately 1 .mu.m/min at a solution temperature of 80.degree. On the other hand, it has been found from the experimental results that there is a relationship as shown in FIG. 7 between the weight concentration of silicon hydroxide in the etching solution and the etching rate. Figure 7 shows that the etching rate is maximum when the hydroxide theoretical weight concentration is 35%, and that if the hydroxide logical weight concentration is 20% or more, a high etching rate of 0.8 μm/min or more can be obtained. . Regarding undercutting at the corners of insulation isolation islands, there is a relationship as shown in Figure 8 between the volume concentration of inpropyl alcohol added to the silica hydroxide aqueous solution as an undercutting inhibitor. It was found that when the density was 15 or more, undercutting was slightly reduced.

第6図、第7図及び第8図から本発明におけるエツチン
グ液としては重量濃度20%以上の水酸化加珪水溶液に
容量比率15%以上のイソプロピルアルコールを添加す
る構成にすることによυアンダーカッテングが少なく高
能率なエツチング速度を有するエツチング条件がめられ
た。該エツチング条件下で絶縁分離島の隅角部のアンダ
ーカッテングを防止するためのエツチングマスクに付加
する角部補償パターンの大きさをめた。第9図は分離V
字溝幅Wに対して必要とする角部補償パターンの大きさ
ノとの相関を示す結果であシ第9図よシ分離V字溝幅W
と角部補償パターンの大きさノの間は!=aw+bなる
相関式で表わすことができる。ここでa、bの項は使用
するアルカリ系エツチング液の組成、濃度、温度によシ
決まる定数であシ本発明のエツチング液でのエツチング
条件下ではaは0.4至乃0.5.bは一9至乃−4の
値となシ角部補償パターンの大きさは 0、4 W −9≦!≦0.5W−4 で表わせる相関を満足する範囲内が最適となった。
From FIG. 6, FIG. 7, and FIG. 8, the etching solution in the present invention has a constitution in which isopropyl alcohol with a volume ratio of 15% or more is added to a silica hydroxide aqueous solution with a weight concentration of 20% or more. Etching conditions with less cutting and a highly efficient etching rate were found. The size of the corner compensation pattern to be added to the etching mask was determined to prevent undercutting of the corner of the isolation island under the etching conditions. Figure 9 shows the separation V
The results show the correlation between the width W of the V-groove and the size of the corner compensation pattern required.
and the size of the corner compensation pattern! It can be expressed by the correlation equation =aw+b. Here, the terms a and b are constants determined by the composition, concentration, and temperature of the alkaline etching solution used. Under the etching conditions using the etching solution of the present invention, a is 0.4 to 0.5. b has a value between 19 and -4, and the size of the corner compensation pattern is 0, 4 W -9≦! The optimum range was found to satisfy the correlation expressed by ≦0.5W-4.

(6)発明の詳細な説明 本発明は以上説明したようにアルカリ系エツチング液と
して水酸化加珪、純水、イングロビルアルコールから力
る組成を有する水溶液とし構築する絶縁分離島のエツチ
ングマスクの隅角部に設ける角部補償パターンの大きさ
を、6=a h+b又は、g=aw−1−bなる関係式
を満足するように構成することにより絶縁分離島の隅角
部のアンダーカッテングを少なくしかつ絶縁分離島の高
密度化をはかることができ半導体集積回路のベレット寸
法を小さくできるため半導体集積回路の製造時の歩留シ
向上と価格を低減させる効果がおる。
(6) Detailed Description of the Invention As explained above, the present invention is directed to etching the corners of an etching mask of an insulating isolation island constructed using an aqueous solution having a composition of silicon hydroxide, pure water, and Inglobil alcohol as an alkaline etching solution. By configuring the size of the corner compensation pattern provided at the corner to satisfy the relational expression 6=a h+b or g=aw-1-b, undercutting at the corner of the insulation isolation island can be reduced. Moreover, it is possible to increase the density of the insulating isolation islands and reduce the pellet size of the semiconductor integrated circuit, which has the effect of improving the yield and reducing the cost during the manufacture of the semiconductor integrated circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は誘電体絶縁分離法による半導体集積回路の部分
断面図、第2図(a)、 (b)、 (C)、 (d)
は各々誘電体絶縁分離基板の製造方法を工程順に示す製
造プロセス図、第3図は異方性エツチング時のエツチン
グマスク下・のアンダーカツテングを示す模形図、第4
図はアンタ“−カツテングを防止するためエツチングマ
スクの外側隅角部を補償型した角部補償パターンを示す
模形図、第5図は第4図に示した補償型にしたエツチン
グマスクの隣接するエツチングマスク間の補償ノ(ター
ンの大きさとエツチングマスク禁止領域との関係を示す
エツチングマスク平面図、第6図は本発明におけるエツ
チング液のエツチングマスクと結晶方位(100)面の
エツチング速度との相関を示す実検結果図、第7図は本
発明におけるエツチング液の水酸化加珪重量濃度とエツ
チング速匿との相関を示す実験結果図、第8図は本発明
におけるエツチング液のインプロピルアルコール添加容
i#L濃度とアンダー力ッテングの大きさを示す実験結
果図、第9図は本発明における第6図、第7図、第8図
の実験結果から得られたエツチングや件下での分離7字
溝幅と角部補償パターンの大きさの最適化を示す相関 
1図、である。 なお図において、1・・・・・・単結晶シリコン基板、
2・・・・・・分離7字溝、3・・・・・・誘電体絶縁
分離膜、4・・・・・・支持体層、5 、5’−・・研
磨面、6・・曲絶縁分離島、7・・・・・・回路素子、
8・・曲エツチングマスク、8a・・・・・・エツチン
グマスク隅角部、9・・・中角部補償パターン、lO・
・・・・・エツチングマスク禁止領域、である。 第3図 第4図 応2図 エラづ一ン7゛液5tシ度〔′C) 水酸イ”tJMi
シ!1寞j町 Q、−ノ第6図 第7図 Iθ 2θ 3θ 40 5θ イソlIaピルアルコール濃度〔φV 第5図 第9図
Figure 1 is a partial cross-sectional view of a semiconductor integrated circuit using the dielectric isolation method, Figure 2 (a), (b), (C), (d)
3 is a manufacturing process diagram showing the manufacturing method of the dielectric insulating isolation substrate in order of process, FIG. 3 is a schematic diagram showing undercutting under the etching mask during anisotropic etching, and FIG.
The figure is a schematic diagram showing a corner compensation pattern in which the outer corner of the etching mask is compensated to prevent under-cutting. Compensation between etching masks (Etching mask plan view showing the relationship between turn size and etching mask prohibited area. Figure 6 shows the correlation between the etching mask of the etching solution in the present invention and the etching rate of the crystal orientation (100) plane. Fig. 7 is an experimental result chart showing the correlation between the silicon hydroxide weight concentration of the etching solution in the present invention and etching speed, and Fig. 8 is a diagram showing the correlation between the etching solution and the etching rate when inpropyl alcohol is added to the etching solution in the present invention. Figure 9 is a diagram showing the experimental results showing the volume i#L concentration and the magnitude of under-force etching. Correlation showing optimization of figure 7 groove width and corner compensation pattern size
Figure 1. In the figure, 1... single crystal silicon substrate,
2...Separation 7-shaped groove, 3...Dielectric insulating separation film, 4...Support layer, 5, 5'--Polished surface, 6...Curve Insulating isolation island, 7...Circuit element,
8... Curved etching mask, 8a... Etching mask corner, 9... Middle corner compensation pattern, lO.
...This is an etching mask prohibited area. Fig. 3 Fig. 4 Fig. 2 Era 17゛Liquid 5t degree ['C] Hydroxic acid tJMi
Shi! 1寞J町Q、-ノFig. 6 Fig. 7 Iθ 2θ 3θ 40 5θ Iso lIa Pyl Alcohol Concentration [φV Fig. 5 Fig. 9

Claims (3)

【特許請求の範囲】[Claims] (1) 単結晶シリコン基板のアルカリ性エツチング液
によるエツチングにおいて、エツチングマスクの隅外部
はアンダーカッテングを抑止する補償型にした角部補償
パターンを有し該角部補償パターンの一辺の大きさノが
分離v字溝幅W又は該分離V字溝幅Wから一義的に決ま
るエツチング深さhとの関係において!= a w +
b又は!=ah−1−bで表わされることを特徴とする
誘電体絶縁分離基板の製造方法。
(1) In etching a single-crystal silicon substrate with an alkaline etching solution, the outside of the corner of the etching mask has a compensation type corner compensation pattern to suppress undercutting, and the size of one side of the corner compensation pattern is separated. In relation to the V-groove width W or the etching depth h that is uniquely determined from the separation V-groove width W! = a w +
b or! =ah-1-b. A method for manufacturing a dielectric insulation isolation substrate.
(2)前記アルカリ性エツチング液紘水酸化論理と純水
とイソプロピルアルコールとを含み、誘電体絶縁分離基
板の製造方法水酸化論理の重量濃度が20−以上である
水酸化論理水溶液に容量比率15チ以上のイソプロピル
アルコールを添加してなるアルカリ性エツチング液であ
ることを特徴とする特許請求の範囲第(1)項記載の誘
電体絶縁分離基板の製造方法。
(2) A method for manufacturing a dielectric insulating isolation substrate, in which the alkaline etching solution contains hydroxide, pure water, and isopropyl alcohol, and the volume ratio is 15 to 15. The method for manufacturing a dielectric insulating isolated substrate according to claim 1, wherein the alkaline etching solution is an alkaline etching solution containing the above-mentioned isopropyl alcohol.
(3)定数aが0.4乃至0.5、定数すが−9乃至−
4であシ、角部補償/くターンの一辺の大きさノが分離
V字溝幅Wとの関係においてQ、4W−9≦ノ≦0.5
 W −4fiる範囲内での相関式 !=a w −1
−bを満足することを特徴とする特許請求の範囲第(1
)項もしくは第(2)項記載の誘電体絶縁分離基板の製
造方法。
(3) Constant a is 0.4 to 0.5, constant Suga is -9 to -
4, the size of one side of the corner compensation/turn is Q in relation to the separation V-shaped groove width W, 4W-9≦≦0.5.
Correlation formula within the range of W -4fi! =aw −1
Claim No. (1) characterized by satisfying -b.
) or (2), the method for manufacturing a dielectric insulating isolation substrate.
JP15386183A 1983-08-23 1983-08-23 Manufacture of dielectric insulator isolating substrate Granted JPS6046033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15386183A JPS6046033A (en) 1983-08-23 1983-08-23 Manufacture of dielectric insulator isolating substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15386183A JPS6046033A (en) 1983-08-23 1983-08-23 Manufacture of dielectric insulator isolating substrate

Publications (2)

Publication Number Publication Date
JPS6046033A true JPS6046033A (en) 1985-03-12
JPH0154855B2 JPH0154855B2 (en) 1989-11-21

Family

ID=15571703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15386183A Granted JPS6046033A (en) 1983-08-23 1983-08-23 Manufacture of dielectric insulator isolating substrate

Country Status (1)

Country Link
JP (1) JPS6046033A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04206522A (en) * 1990-11-30 1992-07-28 Nec Corp Manufacture of semiconductor device
JP2006147946A (en) * 2004-11-22 2006-06-08 Seiko Epson Corp Etching liquid and its production process, and manufacturing process of liquid ejection head
JP2011181770A (en) * 2010-03-02 2011-09-15 Fuji Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04206522A (en) * 1990-11-30 1992-07-28 Nec Corp Manufacture of semiconductor device
JP2006147946A (en) * 2004-11-22 2006-06-08 Seiko Epson Corp Etching liquid and its production process, and manufacturing process of liquid ejection head
JP4552616B2 (en) * 2004-11-22 2010-09-29 セイコーエプソン株式会社 Etching liquid and method for manufacturing the same, and method for manufacturing liquid jet head
JP2011181770A (en) * 2010-03-02 2011-09-15 Fuji Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device
CN102194863A (en) * 2010-03-02 2011-09-21 富士电机控股株式会社 Semiconductor device and method of manufacturing semiconductor device
US9355858B2 (en) 2010-03-02 2016-05-31 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH0154855B2 (en) 1989-11-21

Similar Documents

Publication Publication Date Title
US5767020A (en) Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution
US5492859A (en) Method for producing semiconductor device substrate by bonding a porous layer and an amorphous layer
US4685198A (en) Method of manufacturing isolated semiconductor devices
EP0590876A2 (en) Selective wet etching of silicon and silicon compounds
GB2156149A (en) Dielectrically-isolated integrated circuit manufacture
US4092211A (en) Control of etch rate of silicon dioxide in boiling phosphoric acid
TW441005B (en) Method for producing dual gate oxide layer device
JPH06105797B2 (en) Semiconductor substrate and manufacturing method thereof
US5254494A (en) Method of manufacturing a semiconductor device having field oxide regions formed through oxidation
JPH07176854A (en) Manufacture of device
US6254794B1 (en) Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution
JPS6046033A (en) Manufacture of dielectric insulator isolating substrate
US3725160A (en) High density integrated circuits
US3994817A (en) Etchant for etching silicon
EP0140749B1 (en) Method for producing a complementary semiconductor device with a dielectric isolation structure
CN100565839C (en) The manufacture method of the gate oxide of different-thickness
JP2750163B2 (en) Method of manufacturing dielectric separated semiconductor device
CN113991009A (en) High-selectivity scandium-doped aluminum nitride wet etching process method
KR20050106997A (en) Composition for etching silicon oxide layer and process of etching silicon oxide layer of semi conductor device by using the etchant
CN105655398A (en) Semiconductor structure and forming method thereof
US4691222A (en) Method to reduce the height of the bird&#39;s head in oxide isolated processes
JPS62229843A (en) Anisotropic etching method for semiconductor single crystal
TW201918587A (en) Etching solution composition and etching method using the same
JPS60751A (en) Manufacture of substrate for semiconductor integrated circuit
KR100342861B1 (en) Method for forming isolation of semiconductor device