JPS6045531U - Variable phase pulse generation circuit - Google Patents

Variable phase pulse generation circuit

Info

Publication number
JPS6045531U
JPS6045531U JP1983139531U JP13953183U JPS6045531U JP S6045531 U JPS6045531 U JP S6045531U JP 1983139531 U JP1983139531 U JP 1983139531U JP 13953183 U JP13953183 U JP 13953183U JP S6045531 U JPS6045531 U JP S6045531U
Authority
JP
Japan
Prior art keywords
transistor
voltage
generation circuit
pulse generation
variable phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983139531U
Other languages
Japanese (ja)
Other versions
JPH0246114Y2 (en
Inventor
哲宏 前田
宮前 祥二
細矢 信和
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1983139531U priority Critical patent/JPS6045531U/en
Publication of JPS6045531U publication Critical patent/JPS6045531U/en
Application granted granted Critical
Publication of JPH0246114Y2 publication Critical patent/JPH0246114Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Pulse Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本出願人が先に提案したテレビジョン受像機の
水平同期システムの概略構成を示すブロック図、第2図
はそれに使用した従来の可変位相パルス作成回路を示す
回路図、第3図はその動作説明用の波形図である。第4
図は本考案による可変位相パルス作成回路の一実施例を
示す回路図、第5図はその動作説明用の波形図である。 R1,C1・・・鋸歯状波電圧作成用の抵抗とコンデン
サ、TR4,TR5・・・第1第2のトランジスタ、T
R7,TR8・・・第3第4のトランジスタ、R3・・
・負荷抵抗、R4,R5・・・分圧抵抗、13・・・制
御端子、14・・・出力端子。 第2図 −第3図
Fig. 1 is a block diagram showing a schematic configuration of a horizontal synchronization system for a television receiver that the applicant previously proposed, Fig. 2 is a circuit diagram showing a conventional variable phase pulse generation circuit used therein, and Fig. 3 is a waveform diagram for explaining the operation. Fourth
The figure is a circuit diagram showing an embodiment of the variable phase pulse generating circuit according to the present invention, and FIG. 5 is a waveform diagram for explaining its operation. R1, C1...Resistor and capacitor for creating sawtooth wave voltage, TR4, TR5...First and second transistor, T
R7, TR8...Third and fourth transistor, R3...
- Load resistance, R4, R5... voltage dividing resistor, 13... control terminal, 14... output terminal. Figure 2-Figure 3

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1第2のトランジスタからなる第1差動対と第3第4
のトランジスタからなる第2差動対が構成され、その第
1トランジスタ及び第3トランジスタの各ベースに共通
に一定の繰り返し周期をもつ鋸歯状波電圧i印加し、第
1第4トランジスタの各コレクタを電源に接続した同一
の負荷抵抗に対して共通接続すると共に、前記電源に一
端側が接続された分圧抵抗の他端側に上記電源より゛も
低電圧の可変制御電圧を印加し、上記分圧抵抗の分圧中
点に第2トランジスタのベースを接続し、且つ、第4ト
ランジスタのベースを上記分圧抵抗の他端側に接続し、
前記第1第4トランジスタのコレク、タ共通接続点から
出力パルスを得るようにした可変位相パルス作成回路。
A first differential pair consisting of a first and second transistor, and a third and fourth transistor.
A second differential pair is constructed of transistors, and a sawtooth wave voltage i having a constant repetition period is commonly applied to the bases of the first transistor and the third transistor, and the collectors of the first and fourth transistors are A variable control voltage that is lower than the power source is applied to the other end of the voltage dividing resistor whose one end is connected to the power source, and the voltage is applied to the voltage divider resistor. The base of the second transistor is connected to the voltage dividing midpoint of the resistor, and the base of the fourth transistor is connected to the other end of the voltage dividing resistor,
A variable phase pulse generation circuit configured to obtain an output pulse from a common connection point between collectors and collectors of the first and fourth transistors.
JP1983139531U 1983-09-07 1983-09-07 Variable phase pulse generation circuit Granted JPS6045531U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983139531U JPS6045531U (en) 1983-09-07 1983-09-07 Variable phase pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983139531U JPS6045531U (en) 1983-09-07 1983-09-07 Variable phase pulse generation circuit

Publications (2)

Publication Number Publication Date
JPS6045531U true JPS6045531U (en) 1985-03-30
JPH0246114Y2 JPH0246114Y2 (en) 1990-12-05

Family

ID=30312704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983139531U Granted JPS6045531U (en) 1983-09-07 1983-09-07 Variable phase pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS6045531U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379360A (en) * 1976-12-23 1978-07-13 Matsushita Electric Ind Co Ltd Trigger pulse generating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379360A (en) * 1976-12-23 1978-07-13 Matsushita Electric Ind Co Ltd Trigger pulse generating circuit

Also Published As

Publication number Publication date
JPH0246114Y2 (en) 1990-12-05

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