JPS6045520B2 - Charge transfer type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer type semiconductor device, and more particularly to improving the degree of integration in a device configured to time-divisionally drive a plurality of channels of charge transfer type semiconductor elements.

Charge transfer type semiconductor device (Char CoupledD
When configuring a memory device using CCD (device: CCD), a major issue is how many bits can be integrated per unit area.

Possible methods for increasing the integration density of this CCD memory device include (a) reducing the pattern size and (b) improving the charge transfer method, but even if the charge transfer method is improved, the pattern size cannot be reduced. is even more desirable. As a result, a reduction in the amount of signal charge to be handled is a problem that inevitably arises as CCD memory devices become more highly integrated. In order to detect this minute signal charge, a flip-flop type sense amplifier circuit used in a sense circuit of a dynamic random access memory device is effective. The area occupied by such a sense amplifier circuit in an integrated circuit has a finite size no matter how efficiently it is patterned, and this defines the degree of integration of the CCD memory device.

Therefore, by combining multiple channels of CCD shift registers, making the input/output section of each channel common, and multiplexing the input/output operations in a time-division manner, it is possible to A method is used in which the output signal charge from the CCD shift register is detected. Figure 1 is a block diagram showing a conventional example of a CCD memory device of this type, and 1 is an input n for giving input data.
2 is a channel portion through which charges are transferred; 3 is an output n+ type diffusion region for extracting output charges from each channel portion 2; 4a, 4b, 4c, 4d are channel signals Pa, P, . . . Input gate that is supplied with PO and Pd and performs input multiplexing operation 5X195Y195Z19
5X29 05Yn95Zn, 6 is the transfer gate, 5X
1,5X2..., the first phase transfer signal x is 5
The second phase phase shift signal Y is applied to Y1,...5,,n.
The third phase phase shift signal Z is supplied to Z1, . . . 52n, and the power supply voltage V is supplied to 6.

O is supplied. 7a, 7b, 7c, and 7d are output gates to which channel signals Pa, P, , Pc, and Pd are respectively supplied and perform output multiplexing operations; 8 is a data signal input terminal connected to the input n+ type diffusion region 1; Reference numeral 9 denotes a detection and reproduction circuit for the signal from the output n+ type diffusion region 3.

Now, since the operation of the CCD itself is well known and the operation of the device shown in FIG. 1 in which input/output operations are multiplexed can be easily understood, a brief explanation will be provided.

FIG. 2 is a waveform diagram showing each channel signal and transfer signal that drives this device. First, since the channel signal Pa and the transfer signal By setting the voltage level to the input gate 4a of the a channel, charge is injected into the a channel below the transfer gate 5X1.On the other hand, when the input data signal at this time is "0", the input n
The input gate 4a is set by making the level of the +-type diffusion region 1 sufficiently high.
This prevents signal charges from being injected through the . Also,
At this time point t1, the signal is first injected into the A channel and transferred through the output gate 7a of the A channel. The incoming signal charge is voltage V. Output n from the transfer gate 6 to which D is applied
The signal is output to the +-type diffusion region 3 and introduced into the detection and reproduction circuit 9. At this point, other input gates 4b, 4c
, 4d and output gates 7b, 7c, and 7d are in the off state. Therefore, input/output operations are performed only on the a channel.
Next, at time T2, since the channel signal Pb and the transfer signal X are at a high level, exactly the same operation is performed for the b channel as for the a channel at the above-mentioned time t1. Thereafter, at times T3 and T4, input/output operations for the c channel and d channel are performed in exactly the same way, respectively. In this way, one cycle of input/output multiplexing operations for the four channels is completed at this point, and the signal charges input in this cycle are held for each channel under the transfer gate 5X1. Transfer gate 5x2
, 5x3, . . . , 5xn, signal charges inputted in cycles before this cycle are sequentially held in each channel. Transfer gate 5X1, 5Y2,...
・5Yn, 5.1,522, . . . There is no signal charge under 52n and 6.

Next, at time T6, the transfer signals X and z are at low level and the transfer signal Y is at high level, so signal charges are transferred L for each channel as follows. Then, at time T7, the high level has shifted to the transfer signal Z, so the signal charge is transferred for each channel as follows.

The reason why the signal charge sent downward to the transfer gate 52n spreads to the bottom of the transfer gate 6 is because the transfer gate 6 is always at a voltage of ■C. This is because D is applied.

Then, at time T8, when the transfer signal X changes to a high level, the signal charges are transferred to the transfer gates 5x2, 5X3, . . .
. . 5Xn and 6, the area under the transfer gate 5X1 is cleared in preparation for the next input, and the signal charge to be output next is prepared under the transfer gate 6 of each channel. Thereafter, the cycle from time t1 to time T8 described above is repeated, and the output gates 7a, 7b, 7c and 7
The signal charges are sequentially output to the detection and reproducing circuit for each channel through d. As described above, the configuration shown in FIG. 1 enables multiplexing of CCD memory devices and contributes to higher integration. The insulation gap between adjacent channels of the input and output gates is a major factor that determines the degree of integration of the input/output section, which in turn affects the degree of integration of the CCD memory device. It is desirable that it be as small as possible. However, there is a limit to reducing the size of this insulating gap due to the manufacturing process. Therefore, it is necessary to reduce the number of insulation gaps per unit shift register. The present invention has been made in view of the above-mentioned points, and in an apparatus having a plurality of groups of the above-mentioned devices in which a plurality of channels (CCD shift registers) are multiplexed, the input of mutually corresponding channels in each group is The present invention aims to reduce the number of gate insulating gaps per unit shift register by making the output gates common to each other, thereby obtaining a highly integrated charge transfer type semiconductor device.

FIG. 3 is a block diagram showing an embodiment of the present invention, showing a CCD device composed of two groups k and 1 each consisting of four channels A, b, c and d.

Corresponding channels of both groups are arranged adjacent to each other, and each has a common input gate 4a, 4b, 4.
c and 4d and output gates 7a, 7b, 7c and 7d. In each part, parts belonging to groups k and l are indicated by adding the letters k and l to the reference numerals, respectively. 11k is a metal wiring 1 connecting the input n+ type diffusion regions 1k and the output type diffusion regions 3k of group k;
11 is similar metal wiring for group I, and 12 is their connection point.

The operation of this embodiment device is similar to that of the conventional device described above, so the explanation will be omitted.

As is clear from the figure, in the conventional device shown in Fig. 1, per group [
Input/output gate insulation gap 10 per 91 detection/regeneration circuits
In this embodiment, the number of 3 sets can be reduced to 2 sets. FIG. 4 is a block diagram showing another embodiment of the present invention, in which the completely same idea as the embodiment of FIG.
This is applied to a CCD device composed of four groups of 1 and 2, and the shift gate 5 is somewhat omitted from the illustration.

Since its configuration and operation can be easily understood from the embodiment shown in FIG. 3, the explanation thereof will be omitted. In this embodiment, the number of input/output gate insulation gaps 10 per group is 1.
Can be paired. Of course, the present invention is not limited to the case of a four-channel multiplex as in the above example, and any number of groups may be used in principle.

Furthermore, although the above example shows the case of an n-channel device, it goes without saying that the present invention can also be applied to a p-channel device. As described in detail above, the present invention provides a charge transfer type semiconductor device including a plurality of element groups in which input/output operations of a plurality of channels of charge transfer type semiconductor elements are multiplexed in a time division manner. Since all mutually corresponding channels of the group have common input gates and output gates, the number of insulating gaps between adjacent gates can be reduced, and the degree of integration of this device can be improved. Can be done.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional device, Fig. 2 is a waveform diagram showing each signal driving this device, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a block diagram showing an example of this device. FIG. 3 is a configuration diagram showing another embodiment of the invention.

Claims (1)

[Scope of Claims] 1. In a device comprising a plurality of device groups configured to time-divisionally multiplex the input/output operations of charge transfer type semiconductor devices of a plurality of channels, all mutually corresponding channels of each of the groups 1. A charge transfer semiconductor device characterized in that its input gate and output gate are common. 2. Channels corresponding to each other in all groups are arranged adjacent to each other, and metal wiring is provided to interconnect the signal input sections and signal output sections of all channels belonging to each group. A charge transport type semiconductor device according to claim 1.