JPS6045455B2 - Program progress indicator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program progress display device that displays the order in which a program is executed by a program-controlled computer on a two-dimensional screen.

In order to monitor the program processing status of a computer that is multi-processing multiple programs or to perform program debugging, it is necessary to know the program progress status of the computer.

Conventionally, there are methods using software and methods using hardware to represent the progress of a program.

As a software method, a program having a tracing function (hereinafter abbreviated as tracer) is known. The tracer displays the internal state of the computer on the line printer or character display device each time the computer executes the instructions of the program targeted by the tracer. Alternatively, each time a branch instruction is executed, the memory storage address of the instruction and the type of branch instruction are sequentially displayed on the character display device. Since these methods provide detailed information, they are effective when you have a rough idea of the location of the error. If you are unable to find the error location, there is a huge amount of information and the expression method is an enumeration, so
It is difficult to find the error location. Furthermore, since a large number of tracer instructions are executed every time one instruction of the program to be traced is executed, the processing speed of the program becomes extremely slow. As a result, the timing at which the program exchanges data with the peripheral device differs from the actual operation, making it impossible to detect malfunctions due to timing errors between the computer and the peripheral device that occur when the program is executed. Hardware-based methods include sequentially displaying the memory storage addresses of the instructions that the computer executes on a two-dimensional screen; There is a method in which the scale of the axis corresponds to the size of the lower bits, and as the computer executes the instructions, a point on the screen corresponding to the memory storage address of the instruction is displayed as a dot.

With these methods, it is possible to easily display addresses that should not be executed in a normal program flow, the program flow before and after that address, and the program flow before and after a malfunction. Because the cause of a malfunction often exists long before the malfunction, this method often does not show the cause. Furthermore, if you want to know the flow of a program from the middle of a loop, it is difficult to set a trigger to specify from which address the program should be displayed. SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a display method that allows a computer to easily understand the progress of a program without disturbing the program being executed and without requiring a large memory capacity. The purpose of this invention is to provide a device for displaying images on a two-dimensional screen. The present invention will be described in detail below with reference to the drawings. To know the progress state of a program, it is sufficient to know the order in which the computer executes instructions (hereinafter referred to as the number of steps) and the memory storage address of the executed instructions. In reality, a program is divided into a collection of instructions (hereinafter referred to as blocks) stored in memory without having to check all the instructions one by one, and the instructions in those blocks are executed. The program progress status can also be understood by expressing the order of block names. The minimum set of instructions to be divided into blocks is one instruction, which usually corresponds to a small loop, and the longest one can be considered to be a subroutine unit. Alternatively, it is also possible to divide the program into equal lengths and use each block as a block. Since the method of dividing a program differs depending on the type of error, designation of which instructions are to be made into one block is made from outside the apparatus. FIG. 1 shows an example of the order in which each block is executed.

In FIG. 1, 16 blocks are displayed. Each block is represented along one axis of the screen, and the number of steps corresponds to the other axis. In Figure 1, while an instruction within one block is being executed, the instruction within one block is placed at a position along the vertical axis corresponding to that block and a position along the horizontal axis corresponding to the number of steps at that time. Displayed as a horizontal bar with a length proportional to the number of consecutive executions. Next, when the number of steps increases and instructions in another block are started, a horizontal line with a length proportional to the number of executions will be placed at the vertical axis position corresponding to that block and at the horizontal axis position corresponding to the number of steps. Display as a bar. If an instruction other than the block being displayed is executed, the location corresponding to the number of steps becomes blank. Information necessary for such a display includes the name of the block to which the instructions executed by the computer are distributed and the number of steps indicating how many times the block has been executed consecutively.

Figure 2 shows an example of a memory format. One word of this memory is composed of 8 bits. Since the number of bits required to represent the number of steps successively executed in one block increases or decreases, the number of words required to represent the name of one block and the number of steps executed is indeterminate.

The first bit of the last word in each block is 1, and the first bits of the other words are 0. Part or all of the block name and the corresponding step number are stored in the first word of each block. Therefore, in the example shown in Figure 2, the block name is (4)100)2, and within this block, (B
lr...Blqblp...Blnbl'...Bl
lblO) indicates that the step has been executed twice. Note that the upper and lower bits of the step number are reversed.
This is one way to express it in as few words as possible. The block name to be executed next is (1101)2, and the number of steps required is (B2x...B2sb,...B2
qb2p...B2nb2'...B2lb2O) twice. Note that the subscript of the number indicates the base number. By using the method described above, a huge amount of information can be stored with a small storage capacity, and the program progress status can be easily grasped. FIGS. 3A and 3B are diagrams showing an embodiment of the present invention.

In the figure, 1 and 2 are program-controlled computers that are executing the program in question, and 2 and 3 are program status display devices. 11 is a program counter, which indicates the memory storage address of the instruction being executed by the computer ±■.

A control line 101 is an access signal to the program counter, and the contents of the program counter are updated by this access signal. The control line 102 is the computer ↓
■This is a system clear line that clears the internal state. Every time an access signal is output to the control line 101, the counter 50
1 is added to the contents by the +1 adder 51. The contents of this counter 50 are transmitted to the data processing unit 4 through a signal line 501.
Enters 0. The register 30 takes in the contents of the program counter in synchronization with the access signal on the control line 101 and performs ADR.
It is output to the data processing unit 40 as S. The competition panel 60 specifies externally which address each block corresponds to in the main memory of the computer 10 and outputs the contents to the data processing section 40. 90 is a memory, and the address register 80 indicates the address of the memory 90.

41, 42, 61, and 92 are registers.

The register 42 stores the block name of the instruction executed in the previous step. 43 and 81 are +1 adders, and 93 is a -1 subtracter.

Reference numeral 91 denotes a data converter for converting data into a predetermined storage format.

The data processing unit 40 checks which block the ADRS corresponds to.

If the block name is the same as one step before, +1 adder 4
3 adds 1 to the contents of the register 41, and if they are different, the block name and the contents of the register 41 are supplied to the data converter 91 and converted into the storage format as shown in FIG. 2, and the address register 80 is Write the conversion data to the memory 90 at the specified address.

At the same time, the contents of the register 41 are cleared. Next, the operation of the capturing section will be explained.

The contest panel 60 specifies in the register 61 which address to which address of the main memory of the computer ±■ corresponds to the 16 blocks. Before the computer 1U executes a program, it outputs a system clear signal 102 to clear the contents of the counter 50, the contents of the registers 41 and 61, the contents of the memory 90, etc. The contents of the program counter 11, which represents the storage address in the main memory of the instruction currently being executed by the computer, changes in synchronization with the control line 101. When the access signal is output to the control line 101 as described above, 1 is added to the contents of the counter 50 and the contents of the program counter 11 are taken into the register 30.
The data processing unit 40 compares the contents of the register 61 and the register 30 to find out which block the currently executing instruction belongs to, and temporarily stores it in the register 42.
Compare with the block name before the step. If they are equal, 1 is added to the contents of register 41. If they are different, the contents of the register 41 and the block name are output to the data converter 91, the contents of the register 41 are cleared, and the new block name is stored in the register 42. For example, if the instruction in the third block is executed once and then the instruction in the zeroth block is executed 24 times, a signal of 0301 in the trigonometric number is output to the line 401.

The data conversion unit 91 rearranges the upper and lower bits of the step number sent from the data processing unit 40 and continues it with the block name.

This data is divided into 7-bit units starting from the first bit.
If there is a blank bit at the end, add O to the last 3 to make 7 bits. A 1 is placed as the first bit in the last word, and 0 is placed in the other words. In this way, the second
The data converted into the storage format shown in the figure is output to the memory 90 in order from the first word. 1 in address register 80
, and subtract 1 from register 92. When the contents of register 92 become 0, output is stopped. FIG. 5 shows an example of data conversion when the block name is (3) 16'' and the number of steps is (19D) 16.

As is clear from the figure, if the content of the last word is all O, that word is deleted. The content of the word before it is also all 0.
If so, let's eliminate that word. Do the same below. Therefore, the number of words representing the state is undefined. The memory 90 stores the data sent from the data converter 91 at the address specified by the address register 80. Figure 3A again
, b, the console 60 determines the number of steps to start displaying (hereinafter abbreviated as μSTEP) and the step width in the horizontal axis direction (
(hereinafter abbreviated as W) are the data processing unit 25 and the local memory 3.
Output to 5.

The data processing unit 25 inversely transforms the contents of the memory 90 and S
TEP. The position in the horizontal axis direction is calculated from 5W and output to the local memory 35 along with the professional knock name. The local memory 35 stores the contents of the currently displayed screen in digital form. Unchangeable parts such as character display on the screen are fixedly stored, and block address ranges, STEP. The value of W etc. is written 5 from the console 60, and the content to be displayed in a graph is given from the data processing section 25. The DA conversion circuit 45 outputs an analog signal (bias voltage y1 in the vertical axis direction of the screen, bias voltage 0x in the horizontal axis direction) for displaying the contents of the local memory 35. The signal line 453 is a Z signal, which is a dot brightness modulation signal. On the two-dimensional screen 55, bright spots are displayed at positions corresponding to the signal lines X, y, and z, and characters or graphs are displayed. Register 26 is an address register for memory 90.

The register 28 temporarily stores the total number of steps read from the memory 90 to the data processing section 25. Register 28 is cleared when the content of address register 26 is 0. Next, the operation of this embodiment will be explained using the display screen of FIG. 1 as an example.

When the system clear signal 102 is output, all registers are cleared. When the address range and STE, PlW values, etc. of each block are specified on the console panel 60, those values are output to the data processing section 25 and the local memory 35. The local memory 35 stores block names, their address ranges, STEP and W values, etc. at predetermined addresses. The data processing unit 25 sequentially retrieves one word from the memory 90. If the first bit of one word is 0, then 1 is added to the contents of the address register 26 and the next word is read.

Thereafter, data is read in the same manner until the first bit of one word becomes 2. As shown in FIG. 5, the inverse transformation of the aforementioned transformation is performed on these groups of words, and the block name and step number are read out.

The read number of steps is added to the contents of the register 28 to obtain the total number of steps. The data processing unit 25 uses STEP and w.
Calculate the starting and ending values of the number of steps to display from
When the contents of the register 28 fall within this range, a signal corresponding to the length and position of the horizontal bar to be displayed is output to the local memory 35 and stored therein. The DA conversion circuit 45 converts the contents of the local memory 35 into an analog signal and outputs the bias voltages X,
y and a brightness modulation signal z.

On the secondary screen 55, X sent from the DA conversion circuit 45
, y, and z signals are displayed.
In the example of FIG. 1, the increment width w in the horizontal axis direction is specified as 10, so a plurality of blocks may be displayed in one scale.
As described above, according to the present invention, by displaying the progress state of the program in blocks on a two-dimensional screen, it has become possible to instantly read the general flow of the program.

Therefore, it becomes easier to detect errors that disrupt only one part of the normal flow, which are difficult to find using conventional program debugging methods, or errors that occur during the execution of very long steps or huge loops. It is also useful as a monitor for computers that are processing multiple programs. The present invention is not limited to the above embodiments. Although a compressed storage format is used in the above embodiment, if a high-speed mass storage device is available, the memory storage address can be stored for each step, and the memory storage address for each step from the start of the program to the currently executed instruction can be stored. The total number may also be stored at the same time.

The display method is not limited to horizontal display; if only the order of the blocks in which instructions are executed is important, dot display as shown in FIG. 6 can be considered.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of display by the device of the present invention, and FIG.
The figure shows an example of a storage format used in the device of the present invention, FIGS. 3A and 3B show an embodiment of the present invention, and FIGS. 4 and 5 are examples of data conversion by the device of the present invention. FIG. 6 is a diagram showing another example of display by the device of the present invention.

Claims (1)

[Claims] 1 means for importing the contents of a program counter of a program control computer; means for counting the number of times the contents of the program counter have changed;
means for dividing the contents of the counter into a plurality of blocks and then converting the contents into a predetermined storage format for storage; a display device having a two-dimensional screen for displaying the contents of the storage means; On one axis is the program
A program progress state display device characterized by comprising means for classifying the contents of the counter into each of the blocks and displaying the program progress on the other axis.