JPS6044756B2 - Transfer pulse control method for charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transfer pulse control method for a charge transfer element.

Recently, CCD (Charge-Coupled Dev
ice) is used in various ways.

Application fields of CCDs can be broadly classified into imaging devices, memory devices, analog signal processing devices, and the like. And no matter what field it is applied to, CCDs require transfer pulses. In addition, CCD has a signal charge transfer efficiency of
Since it is greatly affected by the transfer pulse waveform, CCD
It is necessary to supply a transfer pulse with a waveform that matches the characteristics of the In addition, as for the capacity of CCD, taking a two-dimensional sensor as an example, the number of images is 40V x 14H depending on its scale.
(100 to 200 pF for 200 V x 100 H) and 300 to 500 pF for 200 V x 100 H) Furthermore, there is a variation of about 1500 to 5000 pF for 512 V x 340 H. In this way, the electrode capacitance of CCD is currently 2 to 3 depending on its size.
There is twice as much variation. Furthermore, in addition to variations in the capacitance of CCDs, considering fluctuations in power supply voltage, fluctuations in ambient temperature, and process fluctuations, it is impossible to set the amount of signal charge after transfer to 90% or more without a compensation circuit. It's becoming possible. This invention was made in view of the above points, and by temporally matching a plurality of RC time constant circuits consisting of an iCCD drive circuit and a transfer electrode capacitor, a CCD
An object of the present invention is to provide a transfer pulse control system for a charge transfer element that can control the rise time Tr and fall time Tl of a transfer pulse supplied to a charge transfer element.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

First, FIG. 1 shows the simplest circuit for driving a CCD, which is a MOSFET inverter circuit. In FIG. 1, transistor Q1 is a P-channel MOSFET l.
Transistor Q2 is an N-channel MOSFET.
Furthermore, the load capacitance C represents the CCD transfer electrode capacitance. In the drive circuit shown in FIG. 1, the factor that determines the rise time T of the transfer pulse waveform is the 0N
This is a time constant due to resistance and load capacitance CL. Furthermore, the factor that determines the fall time T of the transfer pulse waveform is the time constant due to the ON resistance of the transistor Q2 and the load capacitance CL. In this way, the rise time T and fall time T of the transfer pulse waveform can be controlled by changing the RC time constants in the charging path and the discharging path.
Next, FIG. 2 is a diagram showing the principle of this invention for changing the RC time constant. In FIG. 2, the resistor R1 is the ON resistance of MOSFET Q1 included in the charging path, and the resistor R2 is the ON resistance of MOSFET Q2 included in the discharging path. It also shows that the resistors Rl and R2 can be changed freely by external control voltages. And resistors R1 and R2
As a means for varying the resistance, a method is used in which the values of the resistors R1 and R2 are changed by changing the mutual conductance Gm of the MOSFET included in the charging path and the discharging path of the CCD drive circuit. In addition, normally MOSFE
The mutual conductance g1 of T is given by the following equation. Here, W: channel width, L: channel length, EOx:
Inductivity of SiO2, TOX: Thickness of SiO2
μ: Mobility of MOSFET C,: Gate-source voltage Vth: Threshold voltage of MOSFET And, from equation (1), mutual conductance G of MOSFET. ．． As a parameter to change W/L,.

,,． Although there are various methods of changing the CCD drive circuit, this invention is characterized by temporally combining a plurality of RC time constant circuits each consisting of a MOSFET (7) 0N resistor and a transfer electrode capacitor that constitute a CCD drive circuit. The details will be explained below. Next, FIGS. 3 and 4 are diagrams showing an embodiment of the present invention.

FIG. 3a shows a circuit for controlling the rise time Tr of a transfer pulse, and FIG. 3b shows an input/output timing waveform diagram. Figure 3a
In the transistor Q3, the transistor Q3 is connected in parallel with the transistor Q1, and the input terminal 82 is connected to the gate electrode of the transistor Q3. First, when a low level signal is input to the input terminal 1N1, the transistor Q1 becomes ON, and a charging current flows through the load capacitor CL due to the first RCL time constant. Then, when a low level signal is input to the input terminal 1N1 and a low level signal is input to the input terminal 2, the transistor q becomes 0N, and the second RCL
A charging current flows through the load capacitor CL with a time constant. Next, when a high level signal is input to the input terminal 1N1 and the student power terminal 1N2, the transistor Q2 becomes 0N, and the transistor Q
l, Q3 is turned off. Therefore, the charge stored in the load capacitor CL is discharged through the transistor Q2.
As explained above, in this embodiment, the first J(7)
Compared to the RCL time constant (period in which only transistor Q1 is ON), the second RCL time constant (transistors Q1 and Q3
If the period during which 0N is 0N) is small, the rise characteristic becomes steep during this period, and it is possible to reduce the change in the rise time Tr of the transfer pulse with respect to the change in the load capacitance CL. Next, FIG. 4a shows a circuit for controlling the fall time T of the transfer pulse, and obtains an arbitrary fall time T by temporally controlling two types of RC time constants.

Further, FIG. 4b shows input/output timing waveforms. In FIG. 4a, it has two input terminals 1 and IN2, transistor 9 is connected in parallel to transistor Q2, and input terminal 1N2 is connected to the gate electrode of transistor Q3. First, when a low level signal is input to the input terminals 1N1 and IN2, the transistor Q1 is turned on, the transistors Q12 and Q3 are turned off, and a charging current flows through the load capacitor CL. Next, when a high level signal is input to the input terminal 1N1, the transistor Q2 becomes 0N, and discharging is started with a time constant determined by the 0N resistance of the transistor Ql2 and the load capacitance CL. When a high level signal is input to the input terminal INl, when the input terminal 1N2 becomes a high level signal, the transistors become 0N, and during the period when the transistors Q2 and Q3 are 0N, the second RC
The discharge continues for the L time constant. In addition, in this embodiment, the second RCL time constant (transistor Q2 is 0N) is smaller than the first RCL time constant (period in which only transistor Q2 is ON).
and the period during which Q3 is 0N) is small.

During this period, the falling characteristic becomes steep, and there is an effect that the change in the fall time T of the transfer pulse can be made small with respect to the change in the load capacitance CL. In the above embodiment, only the rise time T of the transfer pulse was controlled in FIG. 3, and the fall time T was controlled in FIG. 4, but it is possible to combine the circuits in FIGS. hand,
By adopting a circuit configuration with two types of RCL time constants, the rise time T and fall time T of the transfer pulse can be reduced.
It is also possible to control f.

As described above, according to this embodiment, even when the load capacitance CL changes greatly, changes in the rise time T and fall time T of the transfer pulse can be controlled better than the circuit configuration with a single RC time constant. Moreover, since the circuit is simple, when integrated into an IC, the chip size can be reduced.

Next, FIGS. 5 and 6 are diagrams showing other embodiments of the present invention.

FIG. 5 shows a circuit that controls the rise time T of the transfer pulse. In the same figure, transistors Q3, Q4, ... Qn are connected in parallel to transistor Q1, and input terminals 1N2, IN3, ... INn are connected to each transistor Q3, Q4, ... Qn, respectively. be done. The operation of the circuit shown in FIG. 5 is the same as that of the circuit shown in FIG. 3, and therefore will not be described here. Next, FIG. 6 shows a circuit for controlling the fall time T of the transfer pulse.

In the figure, transistors Q3, Q4,...Qn are connected in parallel to transistor Q2, and each transistor Q3, Q4, Q, l has an input terminal 1N.
2, IN3, . . . INn are connected. The operation of the circuit shown in FIG. 6 is the same as that of the circuit shown in FIG. 4, so a description thereof will be omitted. In the above embodiment, the rise time Tr of the transfer pulse was controlled in FIG. 5, and the fall time Tf of the transfer pulse was controlled in FIG. By employing a circuit configuration having an RCL time constant, it is also possible to control the rise time Tr and fall time T of the transfer pulse.

As described above, according to this embodiment, even if the load capacitance CL changes greatly, if the pulses input to the plurality of input terminals are selected according to the characteristics of the CCD, the rise time T of the transfer pulse and This has the advantage that the fall time Tf can be controlled without adjustment.

As described in detail above, according to the present invention, by temporally combining a plurality of RC time constant circuits each consisting of a CCD drive circuit and a transfer electrode capacitor in accordance with the characteristics of the CCD, CCD
It is possible to provide a transfer pulse control method for a charge transfer element that can control the rise time Tr and fall time T of a transfer pulse supplied to a CD without adjustment.

[Brief explanation of the drawing]

Figure 1 shows the inverter circuit of MOSFET, Figure 2 shows the inverter circuit of MOSFET.
3A and 3B are diagrams showing a circuit for controlling the rise time Tr of a transfer pulse according to an embodiment of the present invention, and FIGS. 4A and 4B are diagrams illustrating the principle of the present invention. FIG. 5 shows a circuit for controlling the fall time Tf of the transfer pulse.
6 is a diagram showing a circuit for controlling the rise time T of a transfer pulse according to another embodiment of the present invention, and FIG. 6 is a diagram showing a circuit for controlling the fall time T in the same embodiment. .

Claims (1)

[Claims] 1. A plurality of charging/discharging paths are provided in the charge transfer element drive circuit, and the drive of the transistors constituting each charging/discharging path is temporally controlled, and the RC time of charging/discharging is determined by the capacitance of the transistor and the transfer electrode. A transfer pulse control method for a charge transfer device, characterized in that the rise time and fall time of a transfer pulse are adapted to the characteristics of the charge transfer device by combining a plurality of constants.