JPS604344A - Extended control system of transmission line - Google Patents

Abstract

PURPOSE:To prevent loop-back by discriminating a data bit pattern. CONSTITUTION:When a data comes through a line A, a mark state detecting circuit 65 disables a receiver 62 and a driver 64 and sends data received by a receiver 61 to a driver 63, and the driver 63 drives it to a line B. Though the signal driven to the line B is propagated to the receiver 62, the receiver 62 is not operated because it is in the disabled state. Consequently, a mark state detecting circuit 66 judges that data does not come from the line B, and the circuit 66 transmits continuously an enable signal to the receiver 61 and the driver 63.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a transmission line expansion control system, specifically, a transmission line expansion control method that eliminates the loopback phenomenon that occurs when expanding a transmission line in a half-duplex transmission line. System [Technical background of the invention and its problems] Generally, a half-duplex transmission line includes a transmitting circuit/receiving circuit (
Devices having bidirectional drivers/receivers (hereinafter referred to as drivers/receivers) are connected in parallel.

Therefore, the distance of the transmission path and the number of devices that can be connected are limited due to the drive ability of the driver and the receiving sensitivity of the receiver.

Therefore, in order to expand the transmission path, it is conceivable to incorporate an expansion device (hereinafter referred to as a repeater) consisting simply of a driver/receiver, as shown in FIG.

In the figure, I is a processing device, and transmission line 2 (line A
/B) with workstation 3.4.5.

They are the 11 repeaters mentioned above, and line A of transmission path 2.
and B are connected to each other to expand the 1-1 transmission line 2. The internal configuration of the repeaters is as described above, and as shown inside the dotted lines in the figure, drivers
R1, R2).

However, with such a configuration, when data received from line A is transferred to line B, the signal returns to line B, causing a loopback phenomenon in which the data is canceled. Therefore, although the transmission line is extended 1~, the system becomes unreliable. [Objective of the Invention] The present invention has been made in view of the above drawbacks. By controlling the loop phenomenon by determining the data bit pattern that is generated,
The purpose of this invention is to provide a transmission line expansion control system that enables expansion of transmission lines.

[Summary of the Invention] The present invention adds, to the repeater provided for the above reasons, a data bit pattern obtained via a transmission line, a mark state detection circuit for determining whether it is a data frame or a mark state. When it is determined that the frame is a frame, the other driver/receiver (receiver only is fine) is disabled, thereby preventing the loopback phenomenon. When performing transmission using the HDLC procedure, the mark state detection circuit uses a shift register that can shift the data received from the transmission path by seven or more pieces, taking into account the flag, and a shift register that can shift the data received from the transmission path by seven or more consecutive data bits #1. The driver/receiver is configured with a gate that determines whether or not the driver/receiver is enabled and instructs to enable/disable the driver/receiver.

This makes it possible to prevent the loopback phenomenon, and therefore, the transmission line can be expanded with a small amount of hardware without reducing the system efficiency of the half-duplex transmission line.

[Embodiments of the invention]

Hereinafter, using FIG. 2 and subsequent figures, 1. Explain in detail.

The second is a block diagram showing a schematic embodiment of a repeater to which the present invention is adopted. In the figure, 61 is a receiver Rr that receives data obtained via line A, 62 is a receiver R2 that receives data obtained via line B,
63 is a driver that transfers data to line B, 6
4 is a driver that transfers data to line A;

A feature of the present invention is that a mark state detection circuit (DET) is provided between the receiver 61 and the driver 63.

A mark state detection circuit CDET 266) is interposed between the receiver 62 and the driver 64. . . . The signal (EN B 2 ; enable) obtained here is supplied to the receiver 6I and the driver 63. That is, the mark state detection circuit 65 determines whether data is being transferred or not based on the data bit obtained through line A2.When the mark state is in the mark state, the receiver 62
and a circuit for enabling the driver 64.

The mark state detection circuit 66 is a circuit that determines whether data is being transferred or is in a mark state based on the data bit obtained via line B, and enables the receiver 61 and driver 63 when the mark state is present. .

Figure 3 shows HDLC (Hi 1 level Data
2 is an embodiment showing the internal configuration of a repeater when the present invention is adopted for a transmission path using a Link Control procedure.

That is, the mark state detection circuits 65 and 66 are configured to correspond to the data bit pattern of the HDLC procedure.

Components in the figure that have the same numbers or symbols as those in FIG. 2 have the same functions and names as those in FIG. 2, so they will not be described here to avoid duplication. In the figure, 651・
661 is a shift register, and 652j and 662 are AND gates. Shift registers 651 and 661 shift data sent via line A5 and line B, respectively, and their respective outputs are supplied as inputs to AND gates 652 and 662. The AND gate 652 outputs all 11 from the shift register 651.
', the driver 64/receiver 62 is supplied as the enable signal (ENB, ), and the AND gate 662
When all the outputs of the shift register 661 are #1',
Driver 63/receiver 61 Hay enable signal (ENB
, ).

FIG. 4 shows the HDLC device used in the embodiment of the present invention.
The data format of the data bit pattern according to #I is shown.

The operation of the embodiment of the present invention will be explained below.

First, a schematic embodiment shown in FIG. 2 will be explained.

Data is now arriving from either line A/B 1-2
In the non-marked state (marked state), both mark state detection circuits 65 and 66 receive enable signals (BNB, /ENB2).
) is output to the receivers 6I and 62 and drivers 63 and 64.

Next, when data arrives via the line person, mark state detection circuits 6 and 5 disable receiver 62 and driver 64, send the data received by receiver 6I to driver 63, and driver 63 drives to line B.

The signal driven to line B is propagated to the receiver 62, but since it is in the disabled state, the receiver 62 does not operate. Therefore, the mark state detection circuit 6
6 determines that no data is coming from line B, and sends a receiver 61 and driver 63 enable signal (13NB2).
continue to send. Thereafter, when data is about to arrive from line A, the mark state detection circuit 65 determines that the mark state has been reached and outputs a high enable signal (BNB) to the receiver 62 and driver 64.

A similar operation is performed when data is sent from line B.

Next, with reference to FIGS. 3 and 4, the operation when the method of the present invention is implemented on a transmission path of the HD LC procedure will be described in detail.

The data bit pattern is as shown in Figure 4.
In the case of the C procedure, the mark state is always 11', and the maximum number of consecutive flags of 11' in a data frame is six. (Even if there is a bit pattern of all '1's in the data part, 6 (because 0's are inherently inserted, only up to 5 #1's will continue in the data part.) When both are in the mark state, the outputs of the shift registers 651 and 661 are all "1", so the AND gates 652 and 662 both output enable signals to the receivers 6I and 62 and the drivers 63 and 64.

Next, when data arrives via line A, bit '0' at the beginning of the data frame causes shift register 6 to
Since all outputs of 51 are no longer '1', AND gate 65:! The input condition is not satisfied, and the receiver 62 and driver 64 are therefore disabled. The received data output from the shift register 651 is driven to line B via the driver 63. The data driven to line B is propagated to the receiver 62,
Since the receiver 62 is in an enabled state, the receiver 62 does not operate.

Therefore, the mark state detection circuit 661 determines that data is coming from line B. /- Send the enable signal (BNB2) to the driver 61 and driver 63 I) Continue. Since it is unlikely that seven consecutive 11's occur in a data frame, this state continues until the reception of the data frame is completed. Thereafter, when the mark state is entered again, the AND gate 652 enables the receiver 62 and the driver 64. When data arrives via line B, the output from the AND gate 662 is reversed to control the loopback phenomenon as described above.

In the embodiments of the present invention, the HDLC transmission path was described as an example, but the present invention is not limited to this, and the present invention applies to all half-forms that have a data bit pattern that clearly distinguishes whether it is a mark state or a data frame. It can be applied to dual transmission lines. Further, in the embodiment of the present invention, both the driver/receiver on the other side are disabled in order to avoid the loopback phenomenon, but the initial purpose can also be achieved even if only the receiver is disabled.

〔Effect of the invention〕

As described above, according to the present invention, the loopback phenomenon can be prevented, and therefore the transmission path can be expanded without reducing the system efficiency of the half-duplex transmission path and with a small amount of hardware.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the system configuration when the transmission path is expanded, Fig. 2 is a block diagram showing a schematic embodiment of an expansion device (repeater) to which the present invention is adopted, and Fig. 3 is a diagram showing the system configuration when the transmission path is expanded. FIG. 4 is a block diagram showing the internal configuration of a repeater when the present invention is implemented on the transmission path used. FIG. Indicates soto. 6... Expansion device (+l Peter) 57.62... Receiver IR, R2) 63.64...
・Driver (Dr, Dz) 55.66... Mark state detection surface) Raku (D1'mT, , '16.5#, 6
67...Shift register 652.662...ANDGATE applicant's agent Patent attorney Suzue Takehiko 1st figure 132 Hime-3 [::ri-Y! 4!6

Claims (2)

[Claims] (1) In an expansion device provided for transmission path expansion and consisting of a driver/receiver, the data bit pattern obtained via the transmission path is
Added a mark state detection circuit to determine whether it is a mark state,
A transmission line expansion control system characterized in that when a data frame is detected, a receiver on the other side is disabled to prevent loopback. (2) The mark state detection circuit has a shift register capable of shifting at least seven pieces of data received via a transmission line, and the output of the shift register, and detects whether seven or more identical data pits are consecutive. Detect whether or not 1. The other party above
2. The transmission path expansion control system according to claim 1, further comprising a gate for giving an enable/disable instruction to the transmission line.