JPS58186835A - Timing signal selecting system - Google Patents

Timing signal selecting system

Info

Publication number
JPS58186835A
JPS58186835A JP57070996A JP7099682A JPS58186835A JP S58186835 A JPS58186835 A JP S58186835A JP 57070996 A JP57070996 A JP 57070996A JP 7099682 A JP7099682 A JP 7099682A JP S58186835 A JPS58186835 A JP S58186835A
Authority
JP
Japan
Prior art keywords
timing signal
circuit
data
communication control
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57070996A
Other languages
Japanese (ja)
Inventor
Shoji Takahata
高畠　昭次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57070996A priority Critical patent/JPS58186835A/en
Publication of JPS58186835A publication Critical patent/JPS58186835A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To eliminate the need for investigation of the state of a circuit terminating device previously, by detecting selection states of timing signals of the circuit terminating device automatically ad selecting a timing signal automatically according to the detected selection state. CONSTITUTION:While a power source is turned on, a selecting circuit 13 selects a transmission timing signal ST2 from the circuit terminating device. Then, specific transmitted data is set in a transmitted data buffer SB. Consequently, the transmitted data SD is sent back through a switching circuit 17. Namely, the data set in the buffer SB is sent out of a transmitted data shift register R5 to a received data shift register R6 through a circuit 17 to be composed into characters. The composed characters are compared with the data set in the buffer SB by a comparing circuit 16. When they coincide with each other, a signal ST2 is used as the transmission timing signal. When they do not coincide with each other, a register R1 is set to select the transmission timing signal ST1 for its device.

Description

【発明の詳細な説明】 〔発明の分野〕 本発明は通信制御処理装置と回線終端装置とを備えた通
信制御システムにおいて、タイミング信号の選択を自動
的に行う方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for automatically selecting a timing signal in a communication control system including a communication control processing device and a line termination device.

〔従来技術とその問題点〕[Prior art and its problems]

通信制御処理装置と回線終端装置とを備え１回線終端す
置は自装置のタイミング信号と通信制御処理装置からの
タイミング信号とのいずれか一力を選択して動作し１通
信制御処理装置は自装置のタイミング信号と回線終端装
置からのタイミング信号とのいずれか一力を選択して動
作する通信制御システムがある（ＣＣＩ　ＴＴ　−Ｖ２
４）。このタイミング信号は同期式回線をサポートする
場合に使用する。It is equipped with a communication control processing device and a line terminating device, and one line terminating device operates by selecting either the timing signal of its own device or the timing signal from the communication control processing device. There is a communication control system that operates by selecting either the timing signal of the device or the timing signal from the line terminating device (CCI TT-V2).
4). This timing signal is used when supporting synchronous lines.

回線終端装置ではストランプ配線等によりハードウェア
的に固定的に選択が行われ、いずれかのタイミング信号
が使用される。In the line termination device, selection is made in a fixed manner by hardware using strump wiring or the like, and one of the timing signals is used.

−力１通信制御処理装置では制御プ１：ＩグラＪ２等に
より１人手の介入なしにタイミング（ｉ号の選択が可能
ではあるが、システノ・毎にとの回線終端装置がどちら
のタイミング信号を選択するように設定されているかを
、あらかじめ調査して制御プログラムか読めるように設
定しておくことが必要であった。- In the power 1 communication control processing device, the timing (i) can be selected without one person's intervention using control program 1: I graph J2, etc., but the line termination device of each system It was necessary to check in advance to see if it was set to select, and to set the control program so that it could be read.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、このようにシステム毎に異なる各回線
終端装置でのタイミング信号選択状態をハードウェアが
自動的に識別して２通信制御処理装置において正しいタ
イミング信号を自動選択させることにある。An object of the present invention is to enable the hardware to automatically identify the timing signal selection state in each line termination device, which differs from system to system, and to automatically select the correct timing signal in the two communication control processing devices.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明か適用される通信制御システムのブロッ
ク図であり、■は通信制御処理装置、２は回線終端装置
、　ＩＩは回線対応部、　ＳＴＩは通信制御処理装置か
ら回線対応部へ送られる送信タイミング信号、　ＳＴ２
は回線終端装置から通信制御処理装置へ送られる送信タ
イミング信号、　ＲＴは回線終端装置から通信制御処理
装置へ送られる受信タイミング信号、　ＳＤは送信デー
タ信号、１？Ｄは受信データ信号、３は回線である。Fig. 1 is a block diagram of a communication control system to which the present invention is applied, where ■ is a communication control processing device, 2 is a line termination device, II is a line handling section, and STI is a transmission from the communication control processing device to the line handling section. Transmission timing signal, ST2
is the transmission timing signal sent from the line termination device to the communication control processing device, RT is the reception timing signal sent from the line termination device to the communication control processing device, SD is the transmission data signal, 1? D is a received data signal, and 3 is a line.

第２図は回線対応部１１の従来回路例であり、　ＣＬｌ
はクロック源、１２はクロックＣＬＩから送信タイミン
グ信号ＳＴＩを作成する送信速度選択回路、１３は送信
タイミング信号選択回路、　ＲＯは送信タイミング信号
の選択レジスタ、１４．１５は変化検出回路（微分回路
）　、　ＳＢは送信アーク・バッファ、　Ｒ５は送信デ
ータ・シフＩ・・レジスタ、　Ｒ３ば送信ビノトハソフ
ァ、　Ｒ４は受信ビット・バッファ、１？６は受信デー
タ・シフト・レジスタ、　ＲＢは受信データ・ハソ７　
ｙ　、　ＤＶＩ、ＤＶ２はドライバ、　ｌ１ｖｔ−ＲＶ
３はレシーバ、である。FIG. 2 is an example of a conventional circuit of the line correspondence section 11, and CLl
is a clock source, 12 is a transmission speed selection circuit that creates a transmission timing signal STI from the clock CLI, 13 is a transmission timing signal selection circuit, RO is a transmission timing signal selection register, 14.15 is a change detection circuit (differentiation circuit), SB is the transmit arc buffer, R5 is the transmit data shift I register, R3 is the transmit bit buffer, R4 is the receive bit buffer, 1 to 6 is the receive data shift register, RB is the receive data register 7
y, DVI, DV2 are drivers, l1vt-RV
3 is a receiver.

送信タイミング信号の選択レジスタＲＯは制御プログラ
ムによって設定されるが、正しい設定を行うにばあらか
しめ回線終端装置２がどちらを選択しているかを知らね
ばならない。The transmission timing signal selection register RO is set by the control program, but in order to make the correct setting, it is necessary to know which one is selected by the line termination device 2.

第３図は回線終端装置２の回路例であり、　Ｃｌ３はク
ロック源、　２＋はクロックＣＬ２から送信タイミング
信号ＳＴ２を作成する送信速度選択回路、２２ば送信タ
イミング信号選択用のストラップ配線盤。FIG. 3 shows a circuit example of the line termination device 2, in which Cl3 is a clock source, 2+ is a transmission speed selection circuit that creates a transmission timing signal ST2 from the clock CL2, and 22 is a strap wiring board for selecting a transmission timing signal.

２３はその他の回路部である。なお３回線終端装置２ば
本発明にも共通である。23 is another circuit section. Note that the three line termination devices 2 are also common to the present invention.

第４図は本発明の一実施例回路図であり、第２図と同じ
符号は同しものを示し、また１６は比較回路、１７は受
信データ切換回路、　Ｒ１は送信タイミング信号決定レ
ジスタ、　Ｒ２は初期モードレジスタである。FIG. 4 is a circuit diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 2 indicate the same components, 16 is a comparison circuit, 17 is a reception data switching circuit, R1 is a transmission timing signal determination register, and R2 is the initial mode register.

以下に本発明の一実施例の動作を説明する。The operation of one embodiment of the present invention will be described below.

■まず、電源が投入され元状態では、すべてのレジスタ
はりセントされ、従って選択回路１３では回線終端装置
２からのＳＴ２が選択され、また切換回路１７では受信
データ信号ＲＤが選択されている。(1) First, when the power is turned on and in the original state, all registers are loaded, so the selection circuit 13 selects ST2 from the line termination device 2, and the switching circuit 17 selects the received data signal RD.

■電文の送信に先立つで制御プログラムは、初期モード
レジスタＲ２をセットし、かつ送信データ・バッファＳ
Ｂに所定の送信データをセントする。■Prior to transmitting the message, the control program sets the initial mode register R2 and sends the data buffer S.
The predetermined transmission data is sent to B.

これにより送信データＳＤは切換回路１７を介して折り
返される。As a result, the transmission data SD is looped back via the switching circuit 17.

（５） ■即ち、送信データ・バッファＳＢにセットされたデー
タは、送信データ・シフト・レジスタＲ５から１ビツト
づつ送信ビット・バッファＲ３に、送信タイミング信号
ＳＴ２に同期して送出される。(5) (5) That is, the data set in the transmission data buffer SB is sent bit by bit from the transmission data shift register R5 to the transmission bit buffer R3 in synchronization with the transmission timing signal ST2.

送出データＳＤは切換回路１７を介して受信ビット・バ
ッファに受信タイミング信号ＲＴに同期して受信され、
受信データ・シフト・レジスタＲ６よって文字に組み立
てられる。また、１文字が組立ったことにより、レジス
タＲ２をリセットして初期モードを終了する。The sending data SD is received by the receiving bit buffer via the switching circuit 17 in synchronization with the receiving timing signal RT.
The received data is assembled into characters by shift register R6. Furthermore, when one character is assembled, the register R2 is reset and the initial mode is ended.

■組み立てられた文字は受信データ・バッファ日転送さ
れ、送信データ・へソファＳＲにセットされたデータと
比較回路１６で比較される。(2) The assembled characters are transferred to the received data buffer and compared with the transmitted data and the data set in the SR in the comparison circuit 16.

■比較の結果、一致していれば送信タイミング信号とし
てＳＴ２をそのまま用いる。(2) As a result of the comparison, if they match, ST2 is used as is as the transmission timing signal.

■比較の結果、不一致であればレジスタＩ１１をセット
して、送信タイミング信号ＳＴＩを選択する。(2) If the comparison results in a mismatch, register I11 is set and transmission timing signal STI is selected.

なお、比較結果が不一致となるのは、以下の理由による
。The reason why the comparison results are inconsistent is as follows.

回線終端装置２では、　ＳＴＩを選択するときはＳＴ（
６） ２を送出せず（図示実線の状態）、またＳｒ１を選択す
るときにはＳｒ１を通信制御処理装置ｌにも送出する（
図示破線の状態）。従って１回線終端装置２にてＳＴＩ
が選択されていると１回線対応部１１でＳｒ１を選択し
てもレシーバＲＶＩには何も信号が受信されず、よって
受信ヒツト・ハソファＲ３は動作せず同一・の値を出力
し続ける。そのため送信データとは一致しなくなる（た
だし、送信データとしてはオール“′１゛、またはオー
ル“０″以外のデータを用いるものとする）。In line termination equipment 2, when selecting STI, ST (
6) Sr1 is not sent to the communication control processing device l when Sr1 is selected (the state shown by the solid line in the diagram).
state indicated by the broken line). Therefore, STI at one line termination device 2
is selected, no signal is received by the receiver RVI even if Sr1 is selected in the single-line correspondence section 11, and therefore the receiver RVI does not operate and continues to output the same value. Therefore, it does not match the transmission data (however, data other than all "'1" or all "0" is used as the transmission data).

〔発明の効果〕〔Effect of the invention〕

以上のとうり１本発明によれば初期モードによって回線
終端装置のタイミング信号の選択状態を自動的に検出し
、それに合わせて回線対応部でのタイミング信号を自動
選択するので、予め回線終端装置の状態を調査する必要
がな（なる。According to the present invention, the selection state of the timing signal of the line terminating device is automatically detected in the initial mode, and the timing signal in the line corresponding section is automatically selected accordingly. There is no need to investigate the condition.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明が通用される通信制御システムのブロッ
ク図であり、１は通信制御処理装置、２ば回線終端装置
、１１は回線対応部、　ＳＴＩは通信制御処理装置から
回線対応部へ送られる送信タイミング信号、　Ｓｒ１は
回線終端装置から通信制御処理装置へ送られる送信タイ
ミング信号である。 第２図は回線対応部ＩＩの従来回路例であり、１３ば送
信タイミング信号選択回路、　ＲＯは送信タイミング信
号の選択レジスタ、　ＳＢは送信データ・ハソファ、　
１７５は送信データ・シフ１−・レジスタ、　Ｒ３は送
信ヒツトバッファ、　１１４は受信ヒツト・ハソファ、
　１１６は受信データ・シフト・レジスタ、　ＲＢば受
信データ・ハソファである。 第３図は回線終端装置２の回路例であり、２２は送信タ
イミング信号選択用のストラップ配線盤である。 第４図は本発明の一実施例回路図であり、　１６は比較
回路、１７は受信データ切換回路、　Ｒ１は送信タイミ
ング信号決定レジスタ、　Ｒ２は初期モードレジスタで
ある。FIG. 1 is a block diagram of a communication control system to which the present invention can be applied, in which 1 is a communication control processing device, 2 is a line termination device, 11 is a line handling section, and STI is a signal sent from the communication control processing device to the line handling section. Sr1 is a transmission timing signal sent from the line termination device to the communication control processing device. FIG. 2 shows an example of a conventional circuit of the line correspondence section II, where 13 is a transmission timing signal selection circuit, RO is a transmission timing signal selection register, SB is a transmission data selection circuit,
175 is a transmission data shift 1 register, R3 is a transmission hit buffer, 114 is a reception data shift register,
116 is a receive data shift register, and RB is a receive data shift register. FIG. 3 shows a circuit example of the line termination device 2, and 22 is a strap distribution board for selecting a transmission timing signal. FIG. 4 is a circuit diagram of an embodiment of the present invention, in which 16 is a comparison circuit, 17 is a reception data switching circuit, R1 is a transmission timing signal determination register, and R2 is an initial mode register.

Claims (1)

【特許請求の範囲】 通信制御処理装置と回線路αＮ５装置とを（Ａｆ！え１
回線終端装置は自装置のタイミング信号と通信制御処理
装置からのタイミング信号とのいずれか一カを選択して
動作し２通信制御処理装置は自装置のタイミング信号と
回線終端装置がらのタイミング信号とのいずれか一力を
選択して動作する通信制御において。 データ通信に先立って通信制御処理装置はまず回線終端
装置からのタイミング信号を選択するとともに、データ
の送信回路とデータの受信回路とを通信制御処理装置内
部で折り返してデータの送受信をおこない、送信データ
と受信データとの比較を行い、一致している場合はその
まま回線路α１；１装置からのタイミング信号を用いる
ようにし、不一致の場合には自装置のタイミング信号を
選択して用いるよううにしたごとを特徴とするタイミン
グ信号の選択方式。[Claims] A communication control processing device and a circuit line αN5 device (Af!E1
The line terminating device operates by selecting either its own timing signal or the timing signal from the communication control processing device, and the communication control processing device selects either its own timing signal or the timing signal from the line terminating device to operate. In communication control that operates by selecting one of the following. Prior to data communication, the communication control processing device first selects a timing signal from the line termination device, and loops back the data transmission circuit and data reception circuit within the communication control processing device to transmit and receive data. and the received data, and if they match, the timing signal from the circuit line α1;1 device is used as is, and if they do not match, the timing signal of the own device is selected and used. A timing signal selection method characterized by:
JP57070996A 1982-04-27 1982-04-27 Timing signal selecting system Pending JPS58186835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57070996A JPS58186835A (en) 1982-04-27 1982-04-27 Timing signal selecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57070996A JPS58186835A (en) 1982-04-27 1982-04-27 Timing signal selecting system

Publications (1)

Publication Number Publication Date
JPS58186835A true JPS58186835A (en) 1983-10-31

Family

ID=13447670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57070996A Pending JPS58186835A (en) 1982-04-27 1982-04-27 Timing signal selecting system

Country Status (1)

Country Link
JP (1) JPS58186835A (en)

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