JPH03226046A - Monitoring device - Google Patents

Monitoring device

Info

Publication number
JPH03226046A
JPH03226046A JP2020562A JP2056290A JPH03226046A JP H03226046 A JPH03226046 A JP H03226046A JP 2020562 A JP2020562 A JP 2020562A JP 2056290 A JP2056290 A JP 2056290A JP H03226046 A JPH03226046 A JP H03226046A
Authority
JP
Japan
Prior art keywords
section
data
serial data
line
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2020562A
Other languages
Japanese (ja)
Inventor
Hirotsugu Ishikawa
石川 裕嗣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2020562A priority Critical patent/JPH03226046A/en
Publication of JPH03226046A publication Critical patent/JPH03226046A/en
Pending legal-status Critical Current

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  • Small-Scale Networks (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To eliminate the limit of a data length and the mount by sending serially a data sent/received among a central processing section, an input section, an output section, a transmission section, a reception section and a test section or the like on a 2-wire data line via a serial data input output section. CONSTITUTION:A serial data with an address data is sent from a serial data input output section 7 of a central processing section 1 to a data line 13 and transmitted to an input section 2, an output section 3, a transmission section 4, a reception section 5 and a test section 6 or the like. Serial data input output sections 8-12 connecting to each section fetch a serial data only when an address data coincident with an address given to each section is detected from the transmitted serial data via the data line 13 and does not fetch the data in the case of dissidence. Thus, a bus line comprising plural data lines is not required and a limit to a data length sent/received among the sections is not caused and noise due to mutual induction between signals is not generated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は監視制御装置に関し、特に中央処理部、入力部
、出力部、送信部、受信部、試験部等の各部相互間を信
号線で接続しているデータ授受する構成をもつ監視制御
装置に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a supervisory control device, and in particular, to a supervisory control device, in particular a system in which signal lines are used to connect each section such as a central processing section, input section, output section, transmitting section, receiving section, and testing section. The present invention relates to a connected monitoring control device having a configuration for exchanging data.

〔従来の技術〕[Conventional technology]

従来の監視制御装置は、第2図に示すように、中央処理
部14、入力部15、出力部16、送信部17、受信部
18、試験部19を、複数本のデータラインから成るパ
スライン20に接続して、各部間のデータの授受をパス
ライン20上のパラレルデータによって行なうよう構成
される。
As shown in FIG. 2, a conventional supervisory control device connects a central processing section 14, an input section 15, an output section 16, a transmitting section 17, a receiving section 18, and a testing section 19 to a path line consisting of a plurality of data lines. 20, and data is exchanged between each section using parallel data on the path line 20.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このような従来の監視制御袋!では、パスライン20の
本数は各部間で授受されるパラレルデータのビット数だ
け必要であり、各部間で授受するパラレルデータのビッ
ト数に制約を生じ、又バスランイ20上を伝送する信号
の相互誘導により、ノイズを発生し易く、実装配置上の
制約があり、更にパスライン20の伝送距離を長くする
とパラレルデータ間の同期ずれを発生し易くデータの誤
伝送を生ずる等の欠点が有る。
Such a traditional monitoring control bag! In this case, the number of path lines 20 is required to be equal to the number of bits of parallel data sent and received between each section, which imposes restrictions on the number of bits of parallel data sent and received between each section, and also requires mutual guidance of signals transmitted on the bus line 20. Therefore, noise is easily generated, there are restrictions on mounting arrangement, and furthermore, when the transmission distance of the path line 20 is increased, synchronization deviation between parallel data is likely to occur, resulting in erroneous data transmission.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の装置は、監視制御用のデータを授受する複数の
回路部と前記データの処理制御を行なう中央処理部と各
前記回路部および前記中央処理部の相互間で前記データ
を伝送するための信号線とを備えた監視制御装置に於て
、前記信号線はシリアルデータ伝送用の1本のデータラ
インであり、各前記回路部および前記中央処理部は相互
間で該データラインを経由してシリアルデータを授受す
るシリアルデータ入出力部を有している。
The apparatus of the present invention includes a plurality of circuit units that exchange data for monitoring and control, a central processing unit that controls processing of the data, and a system for transmitting the data between each of the circuit units and the central processing unit. In the supervisory control device equipped with a signal line, the signal line is one data line for serial data transmission, and each of the circuit units and the central processing unit communicate with each other via the data line. It has a serial data input/output section that sends and receives serial data.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

第1図に於て、中央処理部1、入力部2、出力部3、送
信部4、受信部5、試験部6はそれぞれシリアルデータ
入出力部7〜12を介して2線式のデータライン13に
接続している。各部間のデータ授受はこのデータライン
13を経由して行なわれる。
In FIG. 1, a central processing section 1, an input section 2, an output section 3, a transmitting section 4, a receiving section 5, and a testing section 6 are connected to a two-wire data line via serial data input/output sections 7 to 12, respectively. It is connected to 13. Data is exchanged between each section via this data line 13.

例えば、中央処理部1のシリアルデータ入出力部7から
はアドレスデータ付きシリアルデータをデータライン1
3に送出し、入力部2、出力部3、送信部4、受信部5
、試験部6等へ伝送される。各部に接続されたシリアル
データ入出力部8〜12は、データライン13を経て伝
送されてくるシリアルデータから各部に付与されたアド
レスと一致するアドレスデータを検出した時にだけその
シリアルデータを取り込み、不一致の時には取り込まな
い、他の各部から送出されるデータも同様にして受信処
理される。なお同報伝送時には、アドレスデータを指定
しなければ良い。
For example, the serial data input/output section 7 of the central processing section 1 sends serial data with address data to the data line 1.
3, input section 2, output section 3, transmitting section 4, receiving section 5
, and transmitted to the testing section 6 and the like. Serial data input/output sections 8 to 12 connected to each section take in the serial data only when they detect address data that matches the address given to each section from the serial data transmitted via the data line 13, and Data sent from other parts, which is not captured at the time of , is also received and processed in the same way. Note that address data need not be specified during broadcast transmission.

本実施例では、複数本のデータラインから成るパスライ
ンを必要とせず、各部相互間で授受するエータ長に対す
る制約は無く、又信号間の相互誘導によって雑音が発生
する事も無いので、実装上の制約も無くなり、装置設計
上の自由度を増大できる。更に、パスライン上で生じる
ようなデータの同期ずれも生じないので、伝送距離の制
約も無くなり、自由度を増大出来る。
In this embodiment, there is no need for a path line consisting of multiple data lines, there is no restriction on the length of data exchanged between each part, and there is no noise caused by mutual induction between signals, so it is easy to implement. This also eliminates the constraints of the above, increasing the degree of freedom in device design. Furthermore, since there is no data synchronization shift that occurs on a path line, there are no restrictions on transmission distance, and the degree of freedom can be increased.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、中央処理部、入力部、出力
部、送信部、受信部、試験部等の間で授受されるデータ
をシリアルデータ入出力部を介して2線式のデータライ
ン上で直列伝送するように構成することにより、データ
長及び実装上の制約を無くし、かつ信号間の相互誘導に
よる雑音を無くす事ができ、更にパスラインの伝送距離
の制約も無くせる効果がある。
As explained above, the present invention transmits and receives data between a central processing section, an input section, an output section, a transmitting section, a receiving section, a testing section, etc. via a two-wire data line through a serial data input/output section. By configuring the above for serial transmission, it is possible to eliminate restrictions on data length and implementation, eliminate noise due to mutual induction between signals, and also eliminate restrictions on transmission distance of path lines. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
従来の監視制御装置のブロック図である。 1.14・・・中央処理部、2,15・・・入力部、3
.16・・・出力部、4.17・・・送信部、5.18
・・・受信部、6.19・・・試験部、7〜12・・・
シリアルデータ入出力部、13・・データライン、20
・・パスライン。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional supervisory control device. 1.14...Central processing unit, 2,15...Input unit, 3
.. 16... Output section, 4.17... Transmission section, 5.18
...Receiving section, 6.19...Testing section, 7-12...
Serial data input/output section, 13...Data line, 20
··Path line.

Claims (1)

【特許請求の範囲】[Claims] 監視制御用のデータを授受する複数の回路部と前記デー
タの処理制御を行なう中央処理部と各前記回路部および
前記中央処理部の相互間で前記データを伝送するための
信号線とを備えた監視制御装置に於て、前記信号線はシ
リアルデータ伝送用の1本のデータラインであり、各前
記回路部および前記中央処理部は相互間で該データライ
ンを経由してシリアルデータを授受するシリアルデータ
入出力部を有していることを特徴とする監視制御装置。
comprising a plurality of circuit units for sending and receiving data for supervisory control, a central processing unit for controlling processing of the data, and a signal line for transmitting the data between each of the circuit units and the central processing unit. In the supervisory control device, the signal line is one data line for serial data transmission, and each of the circuit units and the central processing unit is a serial data line for exchanging serial data between each other via the data line. A supervisory control device characterized by having a data input/output section.
JP2020562A 1990-01-30 1990-01-30 Monitoring device Pending JPH03226046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2020562A JPH03226046A (en) 1990-01-30 1990-01-30 Monitoring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020562A JPH03226046A (en) 1990-01-30 1990-01-30 Monitoring device

Publications (1)

Publication Number Publication Date
JPH03226046A true JPH03226046A (en) 1991-10-07

Family

ID=12030609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020562A Pending JPH03226046A (en) 1990-01-30 1990-01-30 Monitoring device

Country Status (1)

Country Link
JP (1) JPH03226046A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05333980A (en) * 1992-05-28 1993-12-17 Fujitsu Ltd Structure for packaging bus transceiver

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154851A (en) * 1979-05-21 1980-12-02 Hitachi Ltd Data transmission system
JPS5646351A (en) * 1979-09-21 1981-04-27 Ricoh Co Ltd Serial interface device
JPS6135642A (en) * 1984-07-27 1986-02-20 Nissan Motor Co Ltd Network system
JPS6251331A (en) * 1985-08-29 1987-03-06 Mitsubishi Electric Corp On-vehicle electronic control equipment
JPS62181550A (en) * 1986-02-06 1987-08-08 Omron Tateisi Electronics Co Display unit sequential transmission equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154851A (en) * 1979-05-21 1980-12-02 Hitachi Ltd Data transmission system
JPS5646351A (en) * 1979-09-21 1981-04-27 Ricoh Co Ltd Serial interface device
JPS6135642A (en) * 1984-07-27 1986-02-20 Nissan Motor Co Ltd Network system
JPS6251331A (en) * 1985-08-29 1987-03-06 Mitsubishi Electric Corp On-vehicle electronic control equipment
JPS62181550A (en) * 1986-02-06 1987-08-08 Omron Tateisi Electronics Co Display unit sequential transmission equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05333980A (en) * 1992-05-28 1993-12-17 Fujitsu Ltd Structure for packaging bus transceiver

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