JPS604235A - Processing method of semiconductor wafer - Google Patents

Processing method of semiconductor wafer

Info

Publication number
JPS604235A
JPS604235A JP11204483A JP11204483A JPS604235A JP S604235 A JPS604235 A JP S604235A JP 11204483 A JP11204483 A JP 11204483A JP 11204483 A JP11204483 A JP 11204483A JP S604235 A JPS604235 A JP S604235A
Authority
JP
Japan
Prior art keywords
carrier
wafer
semiconductor wafer
jig
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11204483A
Other languages
Japanese (ja)
Inventor
Isao Nishigaya
西ケ谷 勲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11204483A priority Critical patent/JPS604235A/en
Publication of JPS604235A publication Critical patent/JPS604235A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67778Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
    • H01L21/67781Batch transfer of wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To facilitate the automation of transfer operation of a carrier for semiconductor wafer by using a carrier which a semiconductor wafer freely passes through along the grooves having plural V-shaped cross sections formed facing to each other and a jig enabling to carry said carrier and a semiconductor wafer contained in it at a time. CONSTITUTION:Said method uses a semiconductor wafer carrier 11 through which the grooves 5 penetrating with plural V-shaped cross sections formed facing to each other so as to contain plural semiconductor wafers 2 in parallel and with constant intervals, and in which the semiconductor wafers 2 can pass through freely along the grooves 5, and a jig enabling to carry said semiconductor wafer carrier 11 and the semiconductor wafers 2 contained in it at a time. For example, a carrier 10 containing a wafer is put together with an empty carrier 11 by use of the jig. Next, clicks 6 of the jig are opened by operating a handle 7. The wafer 2 is contained in the empty carrier 11 under its own weight, thereby finishing transfer of the wafer.

Description

【発明の詳細な説明】 本発明は半導体つ【ハの処理方式にかかり、とくにIC
,)ランジスタの製1告工程における半導体ウェハ処理
工程で広く一般に使用されている半導体ウェハ用キャリ
ヤ(以後単にキャリヤと呼ぶ)およびそれに使用する治
具に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processing method for semiconductors, and in particular to an IC processing method.
This invention relates to a semiconductor wafer carrier (hereinafter simply referred to as a carrier) that is widely and generally used in a semiconductor wafer processing process in a transistor manufacturing process and a jig used therein.

半導体ウェハ(以後単にウェハと呼ぶ)の処理工程にお
いて、通常ウェハは複数枚が1個のキャリヤに収納され
た状態で各種の化学処理を受ける。
In the process of processing semiconductor wafers (hereinafter simply referred to as wafers), usually a plurality of wafers are housed in one carrier and undergo various chemical treatments.

各々の化学処理においては処理薬液の相互汚染を防ぐ目
的で専用キャリヤが使用される。言い換えれば化学処理
1回終了する毎にギヤリヤからウェハを取り出し、次の
化学処理用の専用ギヤリヤにうつし替えが必ず必委とな
る。
In each chemical treatment, a dedicated carrier is used to prevent cross-contamination of processing chemicals. In other words, every time one chemical treatment is completed, it is necessary to take out the wafer from the gear carrier and transfer it to a dedicated gear carrier for the next chemical treatment.

製造工程におけるハンドリングの自動化を進めるうえで
、キャリヤのうつし替え作業を改善する事が従来大きな
問題となっていた。
In advancing the automation of handling in the manufacturing process, improving the work of changing carriers has traditionally been a major problem.

本発明の目的はキャリヤのうつし替え作沼を自動化しや
すくする為の方式を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for easily automating the replacement of carriers.

本発明の特徴は、複数の半導体ウェハを平行かり等間か
くで収納する為に、互いに対向して形成された複数のv
字型断面を有する溝が各々貝辿し、溝にそって半導体ウ
ェハが通り抜は自在となるような半導体ウェハ用キャリ
ヤと、前記半導体ウェハ用キャリヤと収納されている半
導体ウェハとを同時に持ち運び可能とする治具により構
成される半導体ウェハ処理方式にある。
A feature of the present invention is that in order to store a plurality of semiconductor wafers in parallel and equally spaced, a plurality of
A carrier for semiconductor wafers having grooves each having a letter-shaped cross section and allowing the semiconductor wafer to pass freely along the grooves, and a semiconductor wafer stored in the carrier for semiconductor wafers can be carried at the same time. This is a semiconductor wafer processing method that consists of a jig.

以下図面に従って本発明による一実施例につき詳細に説
明する。第1図は従来使用されているキャリヤの外観図
である。1をまギヤリヤ本体、2は収納されているウェ
ハ、3は断面がV字型の溝である。第2図は第1図のキ
ャリヤの溝部断面を表わす。
An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is an external view of a conventionally used carrier. 1 is a gear rear body, 2 is a wafer stored therein, and 3 is a groove having a V-shaped cross section. FIG. 2 shows a cross section of the groove of the carrier of FIG.

第3図は本発明の実施例によるキャリヤの溝断面を表わ
す。4はキャリヤ本体、5は貫’))l しているv字
型断面を有する溝である。ウェハ2は貫ノmしている溝
5によって保持されているのみである為、キャリヤ本体
4のみを持ち上げればウェハ2は下に残る構造となって
いる。
FIG. 3 represents a groove cross-section of a carrier according to an embodiment of the invention. 4 is a carrier body, and 5 is a groove having a V-shaped cross section. Since the wafer 2 is only held by the penetrating groove 5, the structure is such that if only the carrier body 4 is lifted, the wafer 2 remains below.

第4図は本発明によるキャリヤ運搬治具を表わす。6は
引っかけ部であり、7は取手である。引っかけ部6は取
手7の操作によシ互いに開閉することが出来る。
FIG. 4 represents a carrier transport jig according to the invention. 6 is a hook part, and 7 is a handle. The hook parts 6 can be mutually opened and closed by operating the handle 7.

第5図は治具の使用方法の説明図である。治具の引っか
け部6がキャリヤ4を持ち上げると供にウェハ2がキャ
リヤ4から抜は落ちるのを防ぎ、キャリヤ4とウェハ2
を同時に運搬することが可能となる。
FIG. 5 is an explanatory diagram of how to use the jig. The hook part 6 of the jig lifts the carrier 4 and prevents the wafer 2 from being pulled out from the carrier 4 and falling, thereby separating the carrier 4 and the wafer 2.
It becomes possible to transport both at the same time.

第6図は従来使用されているキビリヤを用いた場合のウ
ェハうりし替え作業を表わす。8は既にウェハを収納し
ているキャリヤであり、9は空のキャリヤである。第6
図(a)の様にまずウェハ収納キャリヤ8上に空のキャ
リヤ9を対称に重ね合せる。次に第6図(b)の様にウ
ェハ収納キャリヤ8、空キャリヤ9を重ね合せたまま上
下を反転させる。
FIG. 6 shows a wafer changing operation using a conventional milling plate. 8 is a carrier that already contains a wafer, and 9 is an empty carrier. 6th
As shown in Figure (a), first, an empty carrier 9 is symmetrically stacked on top of the wafer storage carrier 8. Next, as shown in FIG. 6(b), the wafer storage carrier 8 and the empty carrier 9 are turned upside down while being overlapped.

ウェハ収納キャリヤ8内のウェハ2は自#眞より落下し
空キャリヤ9に収納きれ、ウェハうっし7(1ミえ作業
は終了する。
The wafer 2 in the wafer storage carrier 8 falls from the top and is completely stored in the empty carrier 9, and the wafer removal operation is completed.

第7図は本発明の実箔例によるキャリヤ及び治具による
方式のウェハうつし替え作゛・客を表わす。
FIG. 7 shows a wafer transfer process using a carrier and a jig using an actual foil example of the present invention.

ioは既にウェハを収41)(しているキャリヤで=t
rb、11は空キャリヤである。
io is a carrier that has already received a wafer (41) (=t
rb, 11 is an empty carrier.

第7図(a)の様にまず空キャリヤ11上にウェハを収
納しているキャリヤ10を治具を使J11シて1(ね合
わせる。次に第7図(b)の様に治具の引っかけ部6を
取手7の操作により開く。・ウェハ2は自重によって空
キャリヤIIK収納されウェハうっし替え作業は終了す
る。
As shown in FIG. 7(a), first place the carrier 10 containing the wafer on top of the empty carrier 11 using a jig. The hook part 6 is opened by operating the handle 7. - The wafer 2 is stored in the empty carrier IIK by its own weight, and the wafer replacement work is completed.

本発明によるキャリヤ及び治具により構成されるウェハ
処理方式を用いる事の利点は、第1にウェハうりし替え
作業前後においてキャリヤの姿勢が同一でかつ位置の移
動がない4ト、fj2にキャリヤをつかむ、離すと云う
操作のみでウェハうっし替え作業をイ]うことが出来る
ことである。
The advantage of using the wafer processing method constituted by the carrier and the jig according to the present invention is that, firstly, the posture of the carrier is the same before and after the wafer changing operation, and there is no movement of the position. The wafer reloading operation can be performed simply by grasping and releasing the wafer.

【図面の簡単な説明】[Brief explanation of drawings]

jd’l、’ ]図は従来使mされているキャリヤの外
観図、第2図は第1図のキャリヤの溝部断面図、第3図
は本発明の実に!I例によるキャリヤの溝、it<断面
図、第4図は本発明の実施例によるキャリヤ運搬治具の
外観し1、第5図3ま第4図のキャリヤ運搬治具の使用
方法の説明図、第6図は従来使用されているキャリヤを
用いた場合のウェハのうつし替え作業説明図、第7図は
本発明の実施例による方式のウェハうつ1〜替え作業の
説明図である。 図中、l・・・・・・キャリヤ本体、2・−・・・−収
納されているウェハ、3・・・−・−断面がV字型の溝
、4・・・・・・キャリヤ本体、5・−・・貫i(7:
11ているV字型の?、〜;、6・・・・・・引っかけ
部、7・・・・−・JIX手、8・・・・・・ウェハ収
胛(キャリヤ、9・・・−・・窒キャリヤ、lo・・・
・・・ウェハ収納キャリヤ、11・−・・・空キャリヤ
である。 代理人 弁理士 内 原 音 第2図 第3図 (イ)4図 2 甲5に / (の) (b) 第6図 c死) ■ (b) 7区
Figure 2 is a cross-sectional view of the groove of the carrier shown in Figure 1, and Figure 3 shows the structure of the present invention. FIG. 4 is an external view of a carrier conveying jig according to an embodiment of the present invention, and FIG. 5 is an explanatory diagram of how to use the carrier conveying jig shown in FIGS. 3 and 4. , FIG. 6 is an explanatory diagram of a wafer transfer operation using a conventionally used carrier, and FIG. 7 is an explanatory diagram of a wafer transfer operation according to an embodiment of the present invention. In the figure, l...Carrier body, 2...-Stored wafer, 3...-Groove with a V-shaped cross section, 4...Carrier body , 5 --... Kani (7:
11 V-shaped? , ~;, 6...Hook part, 7...--JIX hand, 8...-Wafer collection (carrier, 9...--Nitrogen carrier, lo...・
. . . wafer storage carrier, 11 . . . empty carrier. Agent Patent Attorney Uchi Hara Oto Figure 2 Figure 3 (A) 4 Figure 2 A5 / (of) (b) Figure 6 c death) ■ (b) District 7

Claims (1)

【特許請求の範囲】[Claims] 枚数の半導体ウェハを平fテかつ笠間かくで収納する為
に、互いに対向して形成された複数のV字型断面を有す
る溝が各々貫通し、溝にそって半導体ウェハが通り抜は
自在となるような半導体ウェハ用キャリヤと、前記半導
体ウェハ用キャリヤと収納されている半導体ウェハとを
同時に持ち運び可能とする治具により構成される半導体
ウェハの処理方式。
In order to store a number of semiconductor wafers on a flat surface with a space between them, a plurality of grooves each having a V-shaped cross section are formed facing each other, and the semiconductor wafers can freely pass through the grooves. A semiconductor wafer processing method comprising a semiconductor wafer carrier and a jig that allows the semiconductor wafer carrier and the stored semiconductor wafer to be carried at the same time.
JP11204483A 1983-06-22 1983-06-22 Processing method of semiconductor wafer Pending JPS604235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11204483A JPS604235A (en) 1983-06-22 1983-06-22 Processing method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11204483A JPS604235A (en) 1983-06-22 1983-06-22 Processing method of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS604235A true JPS604235A (en) 1985-01-10

Family

ID=14576609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11204483A Pending JPS604235A (en) 1983-06-22 1983-06-22 Processing method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS604235A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325721A (en) * 2013-05-20 2013-09-25 扬州晶新微电子有限公司 Rolling type chip moving method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325721A (en) * 2013-05-20 2013-09-25 扬州晶新微电子有限公司 Rolling type chip moving method

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