JPS6041829A - Reception circuit in spread spectrum communication system - Google Patents

Abstract

PURPOSE:To allow the circuit to trace the fluctuation of a correlation peak point of time without reducing S/N by coupling organically a correlation circuit taking correlation between a reception code string and a detection pseudo noise code, a deciding circuit deciding the polarity of an output value of the correlation circuit, a maximum value detection circuit, a ring counter and a storage circuit or the like. CONSTITUTION:The correlation circuit 1 takes correlation between the reception code string and the detection pseudo noise code and a maximum value of its output signal phi(f) is detected by a sample-and-hold circuit 21 in the reception circuit. When a coefficient value of the ring counter is N, a coefficient value (N-1) is stored in (N-1) storage circuits 23, 24 and its content is stored in timing storage circuits 27-29 in response to a signal from a timing signal generating circuit 26. When the content of fetched in latch circuits 31-33 is coincident with the content of the (N-1) storage circuit, a sample signal E is generated, and also an output of a deciding circuit 3 deciding the polarity of the output value of the correlation circuit is fetched in a flip-flop 5 in response to the said sample signal E and outputted as an information data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to an improvement of a receiving circuit in a spectrum I/RAM spread communication system.

(Prior art and its problems) The spread spectrum signal 5(t) used in the spread spectrum communication system J3 is S (j) = d (j) 11 (t) ・co
It is expressed as sωt. Here, d(t) is information data, p(tl is a pseudo-noise code (hereinafter referred to as PN code), and C05O)t is a carrier wave. and,
Information data d(t) and PNN code (t) are (+1.-1
) is a binary signal.

As a receiving circuit that receives this spread spectrum signal S([) and demodulates information data d(t) on the receiving side, for example, the one shown in FIG. 1 is known.

This receiving circuit mainly shows the parts that are the subject of this invention, and it starts from a matched filter circuit (not shown) to a code string d(
Correlation circuit 1 to which t)・p(t> is input, and correlation circuit 1
a comparator circuit 3 for determining whether the output signal φ([>) is positive or negative;
Sampling the peak time of the output signal φ(1),
a ripple signal generation circuit 4 that outputs a sample signal S;
It is composed of a flip-flop 5 that takes in the output of the comparison circuit 3 and outputs information data d(t) in synchronization with the generation timing of the υ sample signal @S.

The above PN code is a code string with M hits as one frame,
The PN code of this one frame corresponds to the code of information data. Therefore, the seasonal number sequence d(t)・
p(t) is a PN code whose polarity is inverted for each frame according to the code of the information data.

The correlation circuit 1 includes a shift circuit 1a which shifts the code string d((〉・p(t)) using a shift clock from a shift clock generator 2 and outputs each tap signal, and a PN of the same type as the transmitting side. A PN code generator 1b that generates a code, and shift [- each tap signal of the circuit 1a and P of the PN code generator 1b]
A plurality of multipliers 1C for multiplying by N code, and each multiplier 1C
and an adder circuit 1d that adds the outputs of and outputs a J signal φ(1) for correlation.

In this correlation circuit 1, code strings d(t), p(t), PN
A correlation with the N code (t) is taken, and the output φ(1) becomes a signal having a sharp peak in the positive direction or in the negative direction, corresponding to the sign of the information data.

This peak point occurs near the boundary of each frame of the PNN code (t).

The sample signal generating circuit 4 is provided with a negative reference level by a comparator circuit 4a which outputs an output when the correlation output φ(1) exceeds a positive reference level, and a -1 multiplier 4b. a comparison circuit 4C that outputs an output when the correlation output φ(1) exceeds the reference level of , and both comparison circuits 4a.
, 4c, and an OR circuit 4d which outputs either one of the outputs of the correlation signal φ(1), samples near the center of the positive peak or near the center of the negative peak of the correlation signal φ(1), and outputs the sample signal S. Output to flip-flop 5.

The flip-flop 5 takes in the output j of the comparator circuit 3 at the timing of the lean pull signal S, and outputs the information data d ((>).

As is well known, in this spread spectrum communication system, the number of bits in one frame of l]N code is
When the power at the correlation peak becomes This is an improvement.In other words, with this method, communication is possible even in the presence of M times the noise.

However, the conventional receiving system is configured to generate a sample signal when the correlation output φ(1) exceeds the reference level, so if noise is superimposed on the correlation output φ(1), the sample signal is There is a risk that this may occur erroneously, and therefore the information data d(t) may not be accurately restored.

Furthermore, since the reference level is set, the signal-to-noise ratio is poor.

The reason why this reception method is adopted despite the drawbacks mentioned above is that it always samples the correlation peak point, so the received code string d(1)・p ([)
has jitter, and even if the correlation peak point changes due to this jitter, it can be easily followed. In other words, S.N.
In order to be able to follow the fluctuations of the correlation peak point without causing a drop in the ratio, it is possible to adopt a PLL, for example, but the circuit configuration becomes complicated and it is difficult to create a receiving circuit that operates easily and reliably. This is because it is difficult.

(Objective of the Invention) An object of the present invention is to easily generate a sample signal by following fluctuations in the correlation peak time without reducing the S/N ratio without reducing the signal-to-noise ratio, and to avoid noise in the correlation output. Jlij has decided to provide a receiving circuit based on the Spectral 18 spread communication system that can reliably generate sample signals of positive V even when the signals are superimposed, thereby restoring information data normally. be.

(Structure and Effects of the Invention) In order to achieve the above objects, the present invention provides a correlation circuit that correlates a received code string with a pseudo noise code for detection, and a determination circuit that determines whether the output value of this correlation circuit is positive or negative. , a maximum value detection circuit for detecting the maximum value of the above-mentioned correlation circuit no.j, a ring counter whose period is one frame of the above-mentioned pseudo-noise code;
1 is stored, and a first window No. 18 that generates a first window No. 18 having a time length corresponding to one frame of the pseudo noise code only once using the output J value of the ring counter. , and after the first window signal disappears, the ring counter becomes N-2.
a second window signal generating circuit that generates a second window signal with a time length corresponding to the number of hours from 4 to N;
[ is a timing signal generation circuit that generates a timing signal when the output value of the correlation circuit exceeds the output value of the maximum value detection circuit within the generation period of the second window signal; a timing memory circuit that stores the contents of the N-1 memory circuit; and a timing memory circuit that captures the content of the timing memory circuit in response to disappearance of the first window signal or the second window signal; -, 1 A lean-pull signal generation circuit that generates a sample signal when the contents of the storage circuit match, and a storage circuit that takes in the output of the judgment circuit and outputs information data in response to this sample signal. It is characterized by

This 4f (according to Nari, the first wind signal or the second
The contents of the ring counter are stored using a timing signal that occurs during the period in which the window signal is generated, and the sample signal to be generated at the next timing is determined based on the stored contents of the ring counter. Therefore, even if there is jitter in the received code string and the peak point of the correlation output fluctuates, the subsequent sample signal generation timing can be determined based on the timing of the fluctuation, so the peak of the correlation output can be easily and reliably determined. It is possible to generate a regular sample signal by following the change in time. Also,
The sample signal is generated within the second window signal generation period, and this second window signal generation period is three pits long of the ring counter. This is 1 of the PN code
Since it is sufficiently small compared to the frame length, in cases where noise is superimposed on the correlation output, not only is there less risk of erroneously generating a sample signal, but the S/N ratio is greatly improved.

(Description of Embodiments) FIG. 2 shows the basic configuration of a receiving circuit according to the present invention, and FIG. 3 shows its operation time charts 1 to 1.

In the figure, this receiving circuit includes the correlation circuit 1° shift 1 to clock generator 2. In addition to the comparison circuit 3 and the flip-flop 5, a sample hold circuit (S/H) 21 detects the maximum value of the output signal φ(1) of the correlation circuit 1;
Above 1) Cycle through one frame of N code! ! A ring counter 22 serving as an IF, latch circuits 23 and 24 to which the contents of the ring counter 22 are sequentially transferred by shifts 1 to clock B from the shift clock generator 2, and the output j value of the ring counter 22 to convert the above PNN. A window signal generation circuit 25 generates a window signal @W1 with a time length corresponding to one frame length once, and the value of the signal A corresponding to the output signal φ(1) exceeds the output value of the sample and hold circuit 21. a timing signal generation circuit 26 that generates a timing signal when the timing signal is generated, and a ring counter 22 . The latch circuits 27, 28 and 29 take in the contents of the latch circuit 23 and the latch circuit 24, respectively, and the contents of the latch circuits 27, 28 and 29 take in the contents of the latch circuits 27, 28 and 29, respectively, at the timing when the output of the inverter 30 is inverted to H level as the signal C disappears. latch circuits 31, 32 and 33, and a matching circuit 34.3 that detects that the contents of latch circuit 23 match the contents of latch circuits 31, 32J> and 33;
5 and 36 basically.

Code string d([)・p which is the input signal to the above correlation circuit 1
(t) is a code string corresponding to information data (110). Note that in the third frame of this code string d(t)·p((), there is jitter (a), and the change point of the code fluctuates.

The output signal φ(1) of the correlation circuit 1 has information data of 111
The maximum value (C) in the positive direction is shown in the first frame and the second frame which are 11, and the maximum value (D) in the negative direction is shown in the third frame where the information data is 'O'.

Note that the small peaks (b) in the first and third frames are mixed noise. This output signal φ(
1) is connected to the ripple hold circuit 21 via the square circuit 37.
and is applied to the timing signal generation circuit 26. In other words, the maximum values included in the output signal A of the square circuit 37 are all in the positive direction, and are inputted to the lean-pull bold circuit 21 and the timing signal generation circuit 26.

The window signal generation circuit 25 includes a ring counter 22
A gate circuit 251 that generates a trigger pulse at the timing when the word number of
The flip-flop 70 tubes 252 and 253 connected vertically, the Q output of the flip-flop 252, and the flip-flop 253
and an AND circuit 254 that generates the window signal W1 under an AND condition with the d output of the window signal W1.
becomes the signal C via the OR circuit 38, which is output to the AND circuit 262 of the timing signal generation circuit 26 and the inverter 3.
0 is input. In addition, flip-flop 252.2
53 is initialized by a signal R8l- from outside the figure to the board 1.

First, since the D input of the flip-flop 252 is connected to the power supply +V, the Q output becomes 1'' level with the first gate pulse output from the gate circuit 251.

At this time, since the ◇ output of the flip-flop 253 is at H level, the AN+) circuit 254 generates the window signal W1.

When the next trigger pulse is input from the gate circuit 251, the flip-flop 252 maintains the Q output at the 1'' level, and the 0 output of the flip-flop 253 becomes the L level. In other words, this wind signal W+ is PN
This is the time equivalent to one frame of the code.

The signal C is composed of the window signal W+ (first) and the window signal W2 (second) created by ORing the output values of -several times ti'834, 35, and 36. This window signal W2 is generated in each frame after the above-mentioned wind signal @W1 disappears, and the ring counter 22
It is the timing of the old teaching from N-2 to NmaC, and the time length is equivalent to 61 hours. That is, the ring counter 22 has a length of 3 bits.

The output j signal E of the minus number circuit 35 is a sample signal applied to the flip-flop 5 via the AND circuit 39, and this ripple signal E is applied to the flip-flop 2 through the AND circuit 39.
This occurs after the Q output of 53 reaches the 1'' level, that is, after the wind signal W1 is turned off, and occurs at the center of the wind signal W2.

The timing signal generation circuit 26 includes a comparison circuit 261 and an A N l) circuit 262. Comparison circuit 26
1 compares the output value of the simple hold circuit 21 with the value of the signal A and hence the output signal φ([). In other words, this comparison circuit 261 has the maximum value (lo) present in the output signal φ(()).
, <C>, and (D), the output is inverted and skipped. Further, the AND circuit 262 outputs the window signal C
When the output of the comparator circuit 261 reaches the 1'' level within the generation period of 1, it is lean-pulled by the shift l-clock B from the shift clock generator 2, and the timing signal is passed to the latch circuits 27, 28 and J. :Give to 29.

First, within the period of occurrence of the first wind signal @W1,
The output signal φ(the two maximum fIil present in ()) corresponding to the 17th frame of the code string d(t)・1)(t), (
Two timings 1a occur at the timing c). Therefore, in the latch times v827, 28 and 29, the ring counter 22 that reaches J3 at the timing of the maximum value (c)
．． The contents of latch circuit 23 and latch circuit 24 are respectively captured. The contents of link counter 22 are now N, and therefore the contents of latch circuits 23,24 are N-18 and N-2, respectively. Latch times i? 82
7 stores N, the latch circuit 28 stores I'm-1, and the latch circuit 29 stores N-2.

Then, at the disappearance of the first window signal W1 and the rise of the output norm of the inverter 30, the latch circuit 27,
The contents of 28J3J and 29 are taken into latch circuits 31, 32 and 33. In other words, the latch circuit 31
Latch circuit 32 connects N-1, and latch circuit $3 connects N-1.
2 respectively.

Then, the timing at which the output values of the latch circuits 31, 32 and 33 and the output value of the latch circuit 23 match is detected in the -number circuits 34, 35 and 36. In other words, the contents of the latch circuit 23 are N-2, N-IJ5 and N
When this happens, the matching circuits 36, 35 and 34 respectively set their outputs to the I'' level.

As a result, the O,R circuit 38 generates a second window signal @W2 corresponding to the second frame. The generation timing of this second window signal W2 is determined by t of the ring counter 22.
Corresponding to the numerical value 1], 83 occurrences occur in the intervals of N-1°N and N+1. Therefore, the n1 number (directly If-1) for detecting a match in the minus number circuit 35 is the timing of the η1 value N of the ring counter, and the output bull signal E is generated at the timing of N.

Furthermore, within the generation period of the second window signal W2 corresponding to the second frame of the code string d([)・p(t), the maximum value (c) of the output signal φ(1) is detected, and the ring A timing signal is output at the timing when the content of the counter 22 is N.

As a result, the same operation as described above is performed, and the second window signal W2 and sample signal E corresponding to the third frame generate Σ. This sample signal, C1[, is generated at the timing when the content of the ring counter 22 is N. In this third frame, a3 is code string d (()・p
<() has jitter (a), so the output signal φ(1
) The timing at which the maximum value (2) occurs is determined by ring counter 2.
The timing of the divisor value of 2 is N+1. That is, the timing signal is generated at timing N-1-1, and the latch circuit 27 stores N+1, the latch circuit 28 stores N, and the latch circuit 29 stores N-1. Therefore, -C1 The second window signal W2 generated in the fourth frame (not shown) is from N-1 to N -+-
The lean pull signal E is generated within 111j of 1, and the lean pull signal E pulls the pull signal at the timing of the divisor value N stored in the latch circuit 23. At this point, the count value of the ring counter is N
+1. In other words, if the generation timing of the correlation output fluctuates, it is possible to quickly follow the fluctuation and generate a regular sample signal.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram mainly showing the part targeted by the present invention among conventional receiving circuits in the spectrum 1 to RAM spread communication systems, and Fig. 2 shows an embodiment of the receiving circuit according to the present invention. Figure 3 shows the operation of the circuit of the above embodiment. 1... Correlation circuit 2... Shift clock generator 3... Comparison circuit 5... Flip-flop 21... Sample hold circuit 22... Link counter 23.24, 27, 28, 29° 31.32.33...Latch circuit 25...Wind signal (first) generation circuit 26...Timing signal generation circuit d(()・p(()...Received code string φ(1)・・
・Correlation circuit output d(t)...Information data 13...Shift 1-clock C...Wind signal D...Timing signal E...Sample Signal Wl...First wind signal W2...Second wind signal Patent applicant Tateishi Electric Co., Ltd.

Claims (1)

[Claims] (1) A correlation circuit that correlates the received code string with the pseudo II tone code for detection, a determination circuit that determines whether the output value of this correlation circuit is positive or negative, and a maximum value detection that detects the maximum value of the output of the correlation circuit. A circuit, a ring counter whose cycle repeats one frame of the pseudo rock (phonetic code), and an N-1 memory circuit in which the count value N-1 is stored when both values of the ring force "Kunta" are N. , the output of the ring counter) j value is used to generate the first window signal with a time length corresponding to one frame of the pseudo-noise code. After the wind signal disappears, the ring counter generates a second window signal having a time length corresponding to the division time at the timing when the ring counter divides the number from N-2 to N. a timing signal generation circuit that generates a timing signal when the output value of the correlation circuit exceeds the output value of the maximum value detection circuit within the generation period of the first window signal or the second window signal; In response to this timing signal, the contents of the N-1 storage circuit are stored (8), and in response to the disappearance of the first window signal or the second window signal, the contents of the timing storage circuit are stored. a sample signal generation circuit that generates a sample signal when the content of the N-1 storage circuit matches the content of the content taken in, and a sample signal generation circuit that takes in the output of the determination circuit in response to the ripple signal and outputs information take. 1. A receiving circuit using a spread spectrum signal system, characterized in that it is equipped with a memory circuit.