JPH04124925A - Correlator - Google Patents

Abstract

PURPOSE:To correctly demodulate transmitted data without being influenced by time difference due to a clock signal by varying and setting detecting time for detecting the peak value of a main lobe appearing at a definite period by a correlation signal obtained by correlation between a DS signal and the same diffusion code as a transmitting side. CONSTITUTION:After every data d0 to dN-1 stored in a shift register 1 is multiplied successively by the same diffusion codes P0 to PN-1 as the transmitting side by a multiplier 2, it is summed successively by a first adder 3, and the correlation signal Vo equivalent to a base band signal is outputted from this first adder 3. At the time of the demodulation of the data, a window setting circuit 6 which can be varied and set by the count value of a counter 6a is provided, and the peak value of the correlation signal Vo exceeding a threshold level Ls (-Ls) is detected while a window is kept in an ON-state. Thus, even if the deviation of the timing arises between the clock signals of the transmitting side and a receiving side, the peak value of the main lobe in the correlation signal Vo can be detected as leaving a margin in the detecting time to some extent, and the data always can stably be demodulated, and reliability is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is used in a spread spectrum communication device used for, for example, radio control of cranes, etc., local communication, confidential communication, etc. This relates to a correlator that decodes a spread DS signal.

[Prior art] Spread spectrum communication has traditionally been used for confidential communication, remote control,
It has been studied in various fields such as local area networks, and has been put into practical use in some cases.

By the way, in spread spectrum communication, in order to decode the received signal, it is necessary to synchronize the transmitting side and the receiving side.
Normally, this type of spread signal is decoded by correlation decoding, one of which is a method using a delay locked loop (DLL).

However, in the case of this DLL method, there are differences in synchronization acquisition time and stable operation, and in recent years, matched filters (
Decoding using an adaptive filter method is attracting attention.

There are two types of matted filters, such as those that use surface acoustic waves (SAW) and those that use digital circuits.They have the advantages of high-speed synchronization and stable operation. The correlation calculation used is expressed by the following formula.

Y (n l ” 'X-' d w ・P + k-
n+where, dk is the input signal, P lk+nl is each bit of the spreading code, and N is the code length of the spreading code.

Therefore, the above equation can be realized by performing the product-sum operation a number of times equal to the code length of the spreading code.

FIG. 3 shows a block configuration of a matched filter that implements the above-mentioned equation using a digital circuit.

In the figure, 15 is a shift register, 16 is a multiplier, 1
7 is an adder. The input signal Vi received from the transmitting side is a DS signal obtained by spreading a baseband signal using a spreading code, and is sequentially input to the shift register 15. Data d stored in the shift register 15. -d, , are each multiplied by the same spreading code as the transmitting side spreading code. That is, each bit P of the spreading code. -P N-1 and multiplier 16
Multiplied by Thereafter, the signals are added by an adder 17 to obtain a correlation signal 0 corresponding to the baseband signal.

When demodulating data by decoding, the correlation is expressed by a main lobe that appears as a peak value at predetermined time intervals and side lobes that appear on both sides of this main lobe, as shown in Figure 2 (b). Of the signal 0, a main lobe exceeding a preset fixed threshold level is detected by a sampling signal every predetermined time (for example, 1/2 chip).

[Problems to be Solved by the Invention] By the way, the time (period) T between each main lobe indicating the peak value appearing in the correlation signal Vo is extremely accurate and constant, but as time passes, the difference between the transmitting side and the receiving side If there is a shift in the timing of the clock signal between the two clock signals, the timing at which the correlation signal V○ is detected may shift, and the main lobe that should be detected cannot be detected from the time difference caused by this clock signal. First, it becomes impossible to demodulate the transmitted data at this time. Furthermore, if all correlation signals VO exceeding the threshold level are determined to be main lobes, the side lobes may exceed the threshold level or the main lobe may not exceed the threshold level due to disturbances, making it impossible to always perform stable data demodulation. There was a problem with the lack of reliability.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to detect the main lobe in a correlation signal without being affected by the time difference caused by the clock signal, and to accurately read transmitted data. The object of the present invention is to provide a highly reliable correlator that can perform demodulation.

[Means for Solving the Problem] In order to achieve the above object, the correlator according to the present invention uses a DS that spreads information data transmitted from the transmitting side with a spreading code.
In a correlator that decodes a signal, a detection time is variably set to detect a peak value of a main lobe that appears at a constant cycle in a correlation signal obtained by correlating the DS signal with the same spreading code as that on the transmitting side. It is characterized by having the means.

[Operation] When a DS signal in which information data is spread with a spreading code is transmitted from the transmitting side and received and detected, the main lobe in the correlation signal that appears at a certain period within a detection time that is variably set in a predetermined range is detected. A peak value is detected.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a correlator according to the present invention.

The correlator according to this embodiment decodes a DS signal in which information data from the transmitting side is spread with a PN code, and includes a shift register 1, a multiplier 2, a first adder 3, a threshold detection circuit 4, a peak Detection circuit 5, window setting circuit 6, state determination circuit 7, first switch circuit 8, second switch circuit 9, switch switching circuit IO1 output device 11. It is configured to include a second adder 12 and a decoder 13.

The shift register l is a signal received and detected from the transmitting side, and is a DS signal Vi which is a baseband signal spread by a spreading code.
are taken in and stored while being shifted sequentially, and the data d0 to d, which are sequentially stored along with the shift operation, are output to the multiplier 2.

The multiplier 2 multiplies the data d o ” d N-1 sequentially inputted from the shift register 1 by the spreading code P.-p s-+, which is the same as the spreading code on the transmitting side. That is, each data d0 to dN-+ for each bit P0 to p of the spreading code
, , , and the results are sequentially output to the adder 3 of the cylinder 1.

The first adder 3 receives each data do -P0 from the multiplier 2.
~dN-1.PH-1 are sequentially added and a correlation signal corresponding to a baseband signal is output to the threshold detection circuit 4, the peak detection circuit 5, and the output device 11.

The threshold detection circuit 4 outputs a status signal rlJ:Sl to one input of the status determination circuit 7 when the level of the input correlation signal exceeds the threshold level.

Note that the threshold level is set in advance to a certain value or higher so that side lobes in the correlation signal Vo are not detected.

The peak detection circuit 5 includes a window setting circuit 6, which will be described in detail later.
Within the window (detection time) set by
The peak value of the main lobe in the correlation signal output from the first adder 3 is detected. In addition, this peak detection circuit 5 outputs an output trigger S2 to a second reset terminal 6d when a count signal of rloIJ is input from a counter 6a, which will be described in detail later, via a second switch circuit 9 during synchronization. The current count value of the counter 6a is reset to "2". Furthermore, this peak detection circuit 5 detects a threshold level Ls (
-Ls), the peak detection signal S3 within the window is output to the second adder 12.

The window setting circuit 6 includes a counter 6a and an OR circuit 6b. The counter 6a sets a window for detecting a correlation signal by counting clock signals, and each time a signal is input to the first reset terminal 6c or the second reset terminal 6d, the counter 6a calculates the current count value. It is reset to a predetermined value and re-counted.

In addition, in this example, the count value [98J to r100J
as count signal S4. S5. While S6 is being output, the window is on and when a signal is input to the first reset terminal 6c, the count value is reset to rOJ, and when a signal is input to the second reset terminal 6d, is configured so that the count value is reset to "2".

The OR circuit 6b has three input terminals connected to the counter 6a.
98” to “100” count signal S4. S5. It is connected to each output terminal that outputs S6, and the output terminals are connected to the peak detection circuit 5 and the state discrimination circuit 7, respectively.

In this OR circuit 6b, "98" to "l" are counted from the counter 6a.
The count signal S4.oo corresponds to the count signal S4. S5. While S6 is input, the state signal rlJ:S7 is output to the peak detection circuit 5 and the state discrimination circuit 7, and while this state signal "l":S7 is output, the peak value of the correlation signal is Wind bow for detection is on.

Note that the on-time of this window can be arbitrarily set by switching the count signal input to the OR circuit 6b.

The state determination circuit 7 is constituted by an AND circuit, one input terminal 7a is connected to the threshold detection circuit 4 and the first switch circuit 8, the other input terminal 7b is connected to the OR circuit 6b, and its output terminal 7c is connected to the first switch circuit 8, the switch changeover circuit 1o, and the output device 11. In this state discrimination circuit 7, when the signals Sl and S7 are inputted from the threshold detection circuit 4 and the OR circuit 6b, an output trigger S8 of the state signal "l" is outputted to the switch changeover circuit 10 and the output device 11. .

The first switch circuit 8 is configured so that either the signal S1 from the threshold detection circuit 4 or the signal S8 from the state discrimination circuit 7 is input to the first reset terminal 6c.
A first contact 8a is connected between the reset terminal 6c and the output of the threshold detection circuit 4;
A second contact 8b is provided between the output of the state determination circuit 7 and the output of the state determination circuit 7.

The second switch circuit 9 is provided between the output terminal of the counter value rl OIJ and the peak detection circuit 5.

The switch changeover circuit 10 has a first switch circuit 8 and a second switch circuit 8.
Switching control is performed in conjunction with the switch circuits 9, and at the time of synchronization supplementation, the first switch circuit 8 is placed on the first contact 8a side,
Further, the second switch circuit 9 is in the off state, and when the status signal rlJ:S8 is input from the status determination circuit 7, the first switch circuit 8 is switched to the second contact 8b side, and the second
The switch circuit 9 is turned on.

The output device 11 outputs a correlation signal to the second adder 12 in response to the output trigger S8 from the state discrimination circuit 7.

The second adder 12 adds the signal S9 from the output device 11 and the signal S3 from the peak detection circuit 5, and outputs the added signal SIO to the decoder 13.

Here, in the correlation signal, a positive peak ■- occurs when the spreading code is synchronized, and a negative peak ■- occurs when there is an anti-correlation.Here, the period of the baseband signal and the period of the spreading code are are set the same, and the positive peak ■+
corresponds to the trailing edge of the baseband signal, and synchronization is achieved at this point, so that decoding is performed in the decoder 13 and data is demodulated.

Next, the operation of the correlator configured as described above will be explained.

During synchronization acquisition in the initial state, the first switch circuit 8
The second switch circuit 9 is in an off state on the contact 8a side.

When the transmitted signal from the transmitting side is detected, the <DS signal Vi is sequentially shifted based on the detected signal and taken into the shift register 1 and stored. Each data d stored in this shift register 1. ~dN-1 is sequentially multiplied by the same spreading codes P0 to PN-1 as on the transmitting side by the multiplier 2, and then sequentially added by the adder 3 of the cylinder 1, and the correlation signal Vo corresponding to the baseband signal is obtained. This first adder 3 outputs the signal.

The correlation signal Vo output from the first adder 3 is output to the threshold detection circuit 4 and the peak detection circuit 5, and in the threshold detection circuit 4, the level of the input correlation signal 0 exceeds the threshold level Ls (-Ls). If it exceeds, the status signal rlJ:sl is output to the status determination circuit 7. Also, the state signal rlJ:Sl at this time is the first
It is also input to the first reset terminal 6C via the switch circuit 8 of , whereby the count value of the counter 6a becomes "
0”.

The counter 6a counts the clock signal, and when the count value reaches [98], a count signal "1" is output to the OR circuit 6b, and the OR circuit 6b outputs a state signal rlJ.
: S7 is output to the peak detection circuit 5 and the state discrimination circuit 7. Status signal rlJ from this OR circuit 6b:S
The output of 7 continues until the count value rloOJ of the counter 6a.

Then, in the peak detection circuit 5, while the count value of the counter 6a is from "98" to rloOJ, that is, while the state signal rlj:S7 is being input from the OR circuit 6b, the window is turned on and the correlation signal is input. Detect the peak value of vO. Moreover, this peak detection circuit 5 detects the correlation signal V exceeding the threshold level Ls (-Ls) within the window.

is not input, a peak detection signal S3 indicating the peak value within the window is output to the second adder 12.

In parallel with this peak value detection operation, the state discrimination circuit 7 outputs a state signal rlJ:S! from the threshold detection circuit 4 and the OR circuit 6b. , S7 is input, the state signal “
1'' is output to the output device 11 as the output trigger S8. Then, when the output trigger S8 is output to the output device 11, the correlation signal 0 is sent to the second adder 1 via the output device 11.
2 is output. This output trigger S8 is also input to the switch changeover circuit 10, whereby the first switch circuit 8 is connected to the second contact 8b side, and the second switch circuit 9 is connected to the second contact 8b side.
are switched on in conjunction with each other.

The second adder 12 performs an addition operation every time the correlation signal Vo is input from the output device 11 in response to the input of the output trigger S8 from the state discrimination circuit 7, and outputs it to the decoder 13.
The decoder 13 decodes the signal SIO sequentially input from the second adder 12 to demodulate data.

Here, when the count value of the counter 6a exceeds the window on time and reaches rloIJ, the count signal Sll at this time is outputted to the peak detection circuit 5 via the second switch circuit 9, thereby causing the peak detection circuit 5, the output trigger S2 is output to the second reset terminal 6d, and the count value of the counter 6a is reset to "2".

Note that if the synchronization code in the data frame is continuously incorrect during the above-mentioned operation, or if an error occurs during error code detection, the decoder 13
0, an error signal S12 is output, which causes
The contacts of the first and second switch circuits 8.9 return to their initial states and the window is released.

Therefore, in the above-mentioned embodiment, when demodulating data, a window setting circuit 6 is provided which can be set variably by the count value of the counter 6a, and the threshold level Ls (-Ls) is set to an extremely low value while the window is on. Since the peak value of the correlation signal ■0 is detected, even if there is a difference in the timing of the clock signal between the transmitting side and the receiving side, the main value of the correlation signal ■0 can be detected with a certain margin of detection time compared to conventional methods. The peak value of the lobe can be detected, and stable data demodulation can be performed at all times, improving reliability.

By the way, the correlator according to the present invention is not limited to the above-described configuration as long as the window can be set by varying the detection time of the correlation signal (2)0.

[Effects of the Invention] As explained above, according to the correlator of the present invention, the main lobe in the correlation signal is detected without being affected by the time difference due to the clock signal between transmission and reception, and transmitted data can be accurately processed. It can be demodulated and reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a correlator according to the present invention, FIGS. 2(a) and (b) are waveform diagrams showing detection outputs and correlation signals, and FIG. 3 is an example of a conventional correlator. FIG. 4... Threshold detection circuit, 5... Peak detection circuit, 6... Window setting circuit, 7... State determination circuit, 8... First switch circuit, 9... Second switch Circuit, IO... Switch switching circuit, VO...
Correlation Patent Applicant Futaba Electronics Co., Ltd. Agent/Patent Attorney Norihiro Nishimura Tip Rod Diagram ■1

Claims (1)

[Claims] In a correlator that decodes a DS signal obtained by spreading information data transmitted from the transmitting side with a spreading code, this is a correlation signal obtained by correlating the DS signal with the same spreading code as that of the transmitting side, and is a main signal that appears at a certain period. A correlator comprising means for variably setting a detection time for detecting a peak value of a lobe.