JPS6041044U - Glass sealed case - Google Patents
Glass sealed caseInfo
- Publication number
- JPS6041044U JPS6041044U JP13329583U JP13329583U JPS6041044U JP S6041044 U JPS6041044 U JP S6041044U JP 13329583 U JP13329583 U JP 13329583U JP 13329583 U JP13329583 U JP 13329583U JP S6041044 U JPS6041044 U JP S6041044U
- Authority
- JP
- Japan
- Prior art keywords
- sealed case
- glass
- glass sealed
- cavity
- die attach
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のガラスマウント用ケースにペレットをマ
ウントした構造を示す断面図、第2図は従来のガラスマ
ウント用ケースに基づくペレット剥離モードを示す拡大
断面図、第3図は従来のガラスマウント用ケースにペレ
ットをマウントした他の構造を示す断面図、第4図は第
3図の従来のガラスマウント用ケースに基づくペレ゛ン
、ト剥離モードを示す拡大断面図、第5図は本考案に基
づくガラスマウント用ケースの実施例を示す断面図、第
6図は第5図のガラスマウント用ケースにペレットをマ
ウントした構造を示す拡大断面図、第7図は本考案に基
づくガラスマウント用ケースに用いるセラミック基体の
斜視図、第8図は第7図の横断面拡大図、である。
なお図において、1・・・セラミック基体、2・・・キ
ャビティ、3・・・ペレット取付用低融点ガラス層、4
・・・低融点ガラス層、5・・・リードフレーム、6・
・・ペレット、7・・・金属膜層、8・・・連続凹凸形
状、である。
第 3 図
第 、5 図Figure 1 is a cross-sectional view showing a structure in which a pellet is mounted in a conventional glass mount case, Figure 2 is an enlarged cross-sectional view showing the pellet peeling mode based on a conventional glass mount case, and Figure 3 is a conventional glass mount case. 4 is an enlarged sectional view showing the pellet peeling mode based on the conventional glass mount case shown in FIG. 3, and FIG. 6 is an enlarged sectional view showing a structure in which pellets are mounted on the glass mount case of FIG. 5, and FIG. 7 is a glass mount case based on the present invention. FIG. 8 is an enlarged cross-sectional view of FIG. 7. In the figure, 1... Ceramic base, 2... Cavity, 3... Low melting point glass layer for pellet attachment, 4
...Low melting point glass layer, 5...Lead frame, 6.
... Pellet, 7... Metal film layer, 8... Continuous uneven shape. Figures 3 and 5
Claims (1)
介してリードフレームを固着して成るガラス封止型ケー
スにおいて、該キャビティー内のダイアタッチ面が複数
個の連続した凹凸形状を有しかつ前記ダイアタッチ面上
に低融点ガラス層を有することを特徴とするガラス封止
型ケース。In a glass-sealed case in which a lead frame is fixed to a ceramic base having a cavity through a low-melting glass, the die attach surface in the cavity has a plurality of continuous uneven shapes, and the die attach A glass-sealed case characterized by having a low melting point glass layer on its surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13329583U JPS6041044U (en) | 1983-08-29 | 1983-08-29 | Glass sealed case |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13329583U JPS6041044U (en) | 1983-08-29 | 1983-08-29 | Glass sealed case |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6041044U true JPS6041044U (en) | 1985-03-23 |
Family
ID=30300733
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13329583U Pending JPS6041044U (en) | 1983-08-29 | 1983-08-29 | Glass sealed case |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6041044U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07201893A (en) * | 1995-01-31 | 1995-08-04 | Sony Corp | Semiconductor device |
-
1983
- 1983-08-29 JP JP13329583U patent/JPS6041044U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07201893A (en) * | 1995-01-31 | 1995-08-04 | Sony Corp | Semiconductor device |
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