JPS6039984B2 - Inspection method for integrated circuit devices - Google Patents

Description

[Detailed description of the invention] The present invention also relates to a method for detecting an integrated circuit device.

Conventionally, when testing a digital IC (LSI), a method has been used in which the initial state of the digital IC is set and then it is determined whether a predetermined output is obtained.

However, some digital ICs cannot have their initial states set externally.

For example, one of the initial states of a flip-flop in an IC is its inverse state, and depending on which state it takes, two types of output patterns are expected, and the initial state can be set externally. If it is impossible or difficult to do so, it is not possible to perform an accurate test simply by comparing one expected value with the output of the digital IC. Therefore, in the present invention, the internal state is uncertain,
The purpose of this invention is to enable an integrated circuit device in which a plurality of types of output patterns are expected to be correctly tested with a minimum number of test steps.

One embodiment of the present invention to achieve the above object is to provide a method for testing a semiconductor integrated circuit device that includes a circuit whose initial state cannot be set externally and produces multiple types of output patterns depending on its initial state. , a plurality of reference circuits from which each of the above output patterns can be obtained is provided in the test circuit system, and the output of the semiconductor integrated circuit device under test is simultaneously compared with the output of each of the above reference circuits, and the output of any of the reference circuits is compared with the output of any of the reference circuits. The feature is to check whether it matches or not.

The present invention will be explained below with reference to Examples.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

1' is a pulse generator POI which can obtain one output pattern expected from the IC to be tested, and 2 is a pulse generator PG2 which can obtain another output pattern expected from the IC to be tested.

3 is an IC to be inspected.

4 and 5 are the output of the IC under test and the pulse generator PG1,
EXCLUSIVE OR circuits 6 and 7 connected so as to compare the outputs of EXCLUSIVE OR circuits 2 and 2 to 0 are connected to an AN for sampling the output of the EXCLUSIVE OR circuits using a strobe signal having a specific period.
D circuits 8 and 9 are Fail Memory (FM1,
2), 10 is an AND circuit for obtaining a logic bond output of the output of FMI and the output of FM2.

Since a normal function tester (function tester) only targets items that have only one type of expected value, the pulse generator "each has only one comparison circuit, but
In this embodiment, since two kinds of expected values, that is, two kinds of output patterns are expected to be tested, the IC 3 is tested, so "two pulse generators, two comparison circuits, and two pulse generators are used depending on the types of expected value patterns." Even if two test circuit systems are installed by providing a fill memory, one output of the test target can be simultaneously tested by the two test circuit systems, and if it passes the test with either test circuit system, it is judged as a good product. Only when both inspection circuit systems fail, the product is determined to be defective.

As a result, a semiconductor integrated circuit device whose internal state is uncertain, where multiple types of output patterns are expected, and whose initial state cannot be set can be tested in a single test process. An example of the time chart in FIG. 2 is shown.

The waveform of the PO turtle changes according to one output pattern, and the P
The waveform of G2 changes according to the other output patterns. If the output pattern of the IC to be inspected matches the output pattern of either PO or PG2, it can be said to be a good product. If it is a good product 1, it matches PG2.If it is a good product 2, it is PG.
It is consistent with I. On the other hand, in the case of defective products, PG
Since it does not match with the military or PG2, the fail signal is AN.
D circuits 6 and 7 are detected, and as a result, a signal is obtained from AND circuit 0 indicating that the product is defective. The circuit device can be tested in a single test process without requiring an external synchronous circuit or the like.

Although the above embodiment deals with a case where two types of output patterns are expected, the number of test circuit systems corresponding to the types of test circuits that are expected to have three or more types of output patterns is also applied. The same test can be performed by preparing the following.

[Brief explanation of drawings]

The first diagram is a test circuit diagram according to an embodiment of the present invention, and the second diagram is a time chart diagram. Military Turtle Umbrella...Pulse General Shout (PG) ``3...IC to be tested''Tsuru, 5...Exclusive OR circuit''
6, 7...AND circuit, 89 9...Fail
Memory (FM entry Hitomi...Failure signal tA...1st
test circuit system, B...second test circuit system. Hair end drawing Tsutomu Z drawing

Claims (1)

[Claims] 1. A method for testing an integrated circuit device that generates a plurality of output patterns in response to an internal state, the method comprising: determining whether a signal corresponding to one of the plurality of output patterns is output to an output terminal of the integrated circuit device; A method for testing integrated circuit devices.