JPS6039826A - Formation of semiconductor active layer - Google Patents
Formation of semiconductor active layerInfo
- Publication number
- JPS6039826A JPS6039826A JP58147532A JP14753283A JPS6039826A JP S6039826 A JPS6039826 A JP S6039826A JP 58147532 A JP58147532 A JP 58147532A JP 14753283 A JP14753283 A JP 14753283A JP S6039826 A JPS6039826 A JP S6039826A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- film
- layer
- insulating film
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000010438 heat treatment Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims abstract description 4
- 230000007547 defect Effects 0.000 claims abstract description 4
- 230000003213 activating effect Effects 0.000 claims description 4
- ZAOJWJAARUYTMA-UHFFFAOYSA-N 4-chloro-2-(5-chloro-2-hydroxy-3-nitrophenyl)sulfanyl-6-nitrophenol Chemical compound C1=C(Cl)C=C([N+]([O-])=O)C(O)=C1SC1=CC(Cl)=CC([N+]([O-])=O)=C1O ZAOJWJAARUYTMA-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 27
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- 229910020286 SiOxNy Inorganic materials 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 6
- 230000004913 activation Effects 0.000 abstract description 4
- 239000012495 reaction gas Substances 0.000 abstract description 3
- 238000005979 thermal decomposition reaction Methods 0.000 abstract description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 23
- 238000005468 ion implantation Methods 0.000 description 15
- 238000007796 conventional method Methods 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003746 solid phase reaction Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- -1 that is Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体活性層、くわしくはガリウム砒素活性層
をイオン注入法によシ形成する方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a semiconductor active layer, particularly a gallium arsenide active layer, by ion implantation.
近年、半導体集積回路（ＩＣと略す）の高速化を目的と
して、ガリウム砒素（ＧａＡｓ と略−Ｊ−）を半導体
として用いた、いわゆるＧａＡｓｌ０の開発が各所で活
発に行なわれている。かかるＧａんＳＩＣの製作におい
ては、ＧａＡｓｌ０の基本素子である電界効果トランジ
スタ、ダイオード等の高性能化を計るために、低抵抗を
実現する高キャリア濃度層の形成方法の開発に大き力努
力が注がれている。従来、かかる高キャリア濃度層の形
成方法として、その均一性、制御性、量産的見地から、
イオン注入法が用いられている。一般に、イオン注入法
においては、注入した不純物を活性化するために熱処理
工程を必要とするが、注入した不純物が、かかる熱処理
工程において熱拡散を起し、イオン注入法の利点である
注入不純物分布の制御性を損うことになる。従って熱処
理工程中において熱拡散係数の小さな不純物を注入不純
物として選択する必要がある。例えば、イオン注入法に
よシ、ｎ形ＧａＡｓ層を形成する場合熱拡散係数の小さ
なシリコン（Ｓｉ＆と略カを用いることが多い。In recent years, with the aim of increasing the speed of semiconductor integrated circuits (abbreviated as IC), so-called GaAsl0, which uses gallium arsenide (GaAs, abbreviated as -J-) as a semiconductor, has been actively developed in various places. In the production of such GaSIC, great efforts are being made to develop a method for forming a high carrier concentration layer that achieves low resistance in order to improve the performance of field effect transistors, diodes, etc., which are the basic elements of GaAsl0. It's broken. Conventionally, from the viewpoint of uniformity, controllability, and mass production, methods for forming such a high carrier concentration layer have been used.
An ion implantation method is used. Generally, the ion implantation method requires a heat treatment process to activate the implanted impurity, but the implanted impurity causes thermal diffusion during the heat treatment process, which is an advantage of the ion implantation method. This will impair controllability. Therefore, it is necessary to select an impurity with a small thermal diffusion coefficient as the implanted impurity during the heat treatment process. For example, when forming an n-type GaAs layer by ion implantation, silicon (Si&), which has a small thermal diffusion coefficient, is often used.
しかしながら、ＳｉはＧａサイトに入ってドナーとなり
、ＡＳサイトに入ってアクセプタとなる不細物すなわち
両性不純物であるため、ｎ形ＧａＡｓ層のイオン注入法
による形成はイオン注入を行なう基体としてのＧａＡｓ
基板の結晶欠陥、例えばストイキオメトリ、微細な結晶
性の影響を受けるとともに、熱処理時における保護膜の
影響とシわけ熱処理時の保護膜とＧａＡｓとの固相反応
もしくは各構成元素の、用互拡散ρ影響を受ける。従っ
て、Ｓｉイオン注入によりｎ形ＧａＡｓ層を形成する場
合、熱処理中に８ｉ０ｚとＧａＡｓとの反応の程度をあ
らかじめ考慮しておき、あえて保護膜として８ｉ０２を
用いるか、あるいは、ＧａＡｓとの反応が非常に少ない
シリコンナイトライド（ｓｉｌＮ４と略す）を保護膜と
して用いることが多い。しかしながら、５ｉ０２保膿膜
を用いた場合には、ＧａＡｓの構成元素であるＧａがＧ
ｉ ０２中を拡散するために、熱処理中にＧ ａ Ａ
ｓのストイキオメトリが大きくくずれ、結晶性を損う
ためにかえって注入した８ｉの活性化を阻む要１となる
。一方、Ｓｉ３Ｎ４保獲膜を用いた場合には、熱処理中
において、ＧａがＳｉ３Ｎ４中に拡散することがないた
めに、注入されたＳｉがＧａザイトを占拠する確率が小
さくなシ、注入したＳｉの活性化率が向上しない原因と
なっている。However, since Si is an impurity, i.e., an amphoteric impurity, which enters the Ga site and becomes a donor and enters the AS site and becomes an acceptor, the formation of an n-type GaAs layer by ion implantation is difficult because Si is a GaAs substrate for ion implantation.
In addition to being affected by crystal defects in the substrate, such as stoichiometry and fine crystallinity, it is also affected by the effect of the protective film during heat treatment, the solid phase reaction between the protective film and GaAs during wrinkle heat treatment, or the interaction of each constituent element. Affected by diffusion ρ. Therefore, when forming an n-type GaAs layer by Si ion implantation, the degree of reaction between 8i0z and GaAs during heat treatment should be considered in advance, and 8i02 should be intentionally used as a protective film, or if the reaction with GaAs is extremely strong. Silicon nitride (abbreviated as silN4), which has a small amount of silicon, is often used as a protective film. However, when using the 5i02 purulent membrane, Ga, which is a constituent element of GaAs, is
During heat treatment, G a A
The stoichiometry of s is greatly disrupted, and this becomes the key point 1 that impedes the activation of 8i, which is implanted to impair crystallinity. On the other hand, when a Si3N4 retention film is used, Ga does not diffuse into Si3N4 during heat treatment, so the probability that the implanted Si occupies the Gasite is small. This is the reason why the activation rate does not improve.
本発明の目的は、イオン注入法により高い活性化率を達
成することができる半導体活性層形成方法を提供しよう
とすることにある。An object of the present invention is to provide a method for forming a semiconductor active layer that can achieve a high activation rate using an ion implantation method.
本発明によれば化合物半導体基板に不純物をイオン注入
せしめた後、これを熱処理によって活性化せしめて半導
体活性層を形成する方法において、化合物半導体の一面
にシリコンオキシナイトライド膜を被着させて熱処理を
行ない、前記化合物半導体基板内にあらかじめ結晶欠陥
を形成した後前記不純物をイオン注入せしめ、これを熱
処理によって活性化せしめることを特徴とする半導体活
性層の形成方法が得られる。According to the present invention, in a method of ion-implanting impurities into a compound semiconductor substrate and then activating it by heat treatment to form a semiconductor active layer, a silicon oxynitride film is deposited on one surface of the compound semiconductor and then heat-treated. A method for forming a semiconductor active layer is obtained, which comprises forming crystal defects in the compound semiconductor substrate in advance, then ion-implanting the impurity, and activating the impurity by heat treatment.
以下に本発明の一実施例を従来方法による例と対比させ
て説明する。第１図は本発明の一実施例を説明するため
の図で、第２図は従来例を説明するだめの図である。第
１図、第２図において、１は半絶縁性Ｇ ａ Ａ Ｓ
％ ２は第１の絶縁膜、３はＳｉイオン注入層、４は第
２の絶縁膜、５はｎ形Ｇ ａ Ａ ｓ層、６は保護膜で
ある。、従来の方法は第１図（ａ）に示すように、まず
半絶縁性Ｇ ａ Ａ ｓ １にＳｉイオンを注入しＳｉ
イオン注入層３を作り次に、第２図（ｂ）に示すように
Ｓｉイオン注入層３を覆って、例えば５ｉ０２もしくは
Ｓｉ３Ｎ４なる保頴膜６を被着した後、第１図（Ｃ）に
示すように、例えば８５０℃ １５分の条件で熱処理を
行ないＳｉイオン注入層３をｎ形ＧａＡｓ層５に変換す
る。An embodiment of the present invention will be described below in comparison with an example using a conventional method. FIG. 1 is a diagram for explaining one embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional example. In Figs. 1 and 2, 1 is semi-insulating G a A S
% 2 is a first insulating film, 3 is a Si ion implantation layer, 4 is a second insulating film, 5 is an n-type GaAs layer, and 6 is a protective film. As shown in FIG. 1(a), the conventional method is to first implant Si ions into the semi-insulating GaAs 1.
After forming the ion implantation layer 3 and depositing a protective film 6 of, for example, 5i02 or Si3N4 to cover the Si ion implantation layer 3 as shown in FIG. 2(b), as shown in FIG. 1(C). As shown, the Si ion implanted layer 3 is converted into an n-type GaAs layer 5 by heat treatment at 850° C. for 15 minutes, for example.
これに対して本発明による方法は、先ず第２図（ａ）に
おいて、まず、半絶縁性ＧａＡｓ１上にシリコンオキシ
ナイトライド（ＳｉＯｘＮｙと略す）なる第１の絶縁膜
２を被着する。８ｉ０ｘＮｙは通常モノシラン（ＳｉＨ
４と略す）−アンモニア（Ｎ）Ｉ ３と略す）−酸素（
０２と略す）の反応ガス系を用いて、熱分解法により６
５０℃〜７００℃の温度で半絶縁性Ｇ ａ Ａ ｓ上に
被着されるが、Ｓ ｉ Ｈ４、ＮＨ３に対する０２の流
量比を変えることによりＳｉＯｘＮｙのＸの値を０から
２まで、一方ｙの値を百から０まで変化させ、ＳｉＯｘ
Ｎｙの組成を制御することができる。次に、例えば８０
０℃、２０分の熱処理を行々うと、半絶縁性Ｇ ａ Ａ
、ｓの構成元素の１つであるＧａが熱処理中に８ｉ０ｘ
Ｎｙを通して拡散し半絶縁性ＧａＡｓ中にＧａの空孔を
残す。このＳｉＯｘＮｙを通して出るＧａＯ量は、主に
ＳｉＯｘＮｙの中の酸素０の量すなわちＸの景に依存し
、Ｘの値が大きい程Ｇａは放出され易くなる。従ってＳ
ｉＯｘＮｙの中のＸを適尚に制御することによりＧａの
空孔の量を制御しうる。実用的にはＳｉＯｘＮｙの組成
を測定評価しなくともＳｉＯｘＮｙの２つの特定の膜す
なわちＳｉＯ”２と８ｉａＮ４との屈折率の間にＳｉＯ
ｘＮｙ の組成の屈、１７ｊ率は分布し、０が多いほど
５ｉ０２の屈折率１．４５に近づき、Ｎが多い程Ｓｉ３
Ｎ４の屈折率２．０に近づくため、８ｉ０ｘＮｙの屈折
率をモニターとして用いることができる。In contrast, in the method according to the present invention, first, as shown in FIG. 2(a), a first insulating film 2 made of silicon oxynitride (abbreviated as SiOxNy) is deposited on the semi-insulating GaAs 1. 8i0xNy is usually monosilane (SiH
4) - Ammonia (N) I 3) - Oxygen (
6 by the pyrolysis method using a reaction gas system (abbreviated as 02).
Deposited on semi-insulating GaAs at temperatures between 50 and 700 degrees Celsius, the value of X of SiOxNy can be varied from 0 to 2 while changing the value of By changing the value of from 100 to 0, SiOx
The composition of Ny can be controlled. Next, for example, 80
When heat treatment is performed at 0°C for 20 minutes, semi-insulating Ga A
, Ga, one of the constituent elements of s, becomes 8i0x during heat treatment.
Diffusion through the Ny leaving Ga vacancies in the semi-insulating GaAs. The amount of GaO released through this SiOxNy mainly depends on the amount of oxygen 0 in SiOxNy, that is, the aspect of X, and the larger the value of X, the easier Ga is released. Therefore, S
By appropriately controlling X in iOxNy, the amount of Ga vacancies can be controlled. Practically speaking, even if the composition of SiOxNy is not measured and evaluated, there is a difference between the refractive index of two specific films of SiOxNy, that is, SiO"2 and 8iaN4.
The refractive index of the composition of xNy is distributed, and the more 0 there is, the closer it is to the refractive index of 5i02, 1.45, and the more N, the more Si3
Since the refractive index of N4 approaches 2.0, the refractive index of 8i0xNy can be used as a monitor.
次に、第２図←）に示すように、第１の絶縁膜を通して
、もしくは、第１の絶縁膜を除去して後２９Ｓｉ＋４オ
ン１１５０ＫｅＶのエネルギーでドーズ景７Ｘ１０１３
ｃｍ−２注入し、Ｓｉイオン注入層３を形成する。次に
第２図（Ｃ）に示すようにＳｔイオン注入層をＳｉ３Ｎ
４なる第２の絶縁膜を被着する。Next, as shown in Fig. 2 ←), the dose profile 7X1013 is applied through the first insulating film or after removing the first insulating film, using 29Si+4 on with an energy of 1150 KeV.
cm-2 is implanted to form a Si ion implantation layer 3. Next, as shown in FIG. 2(C), the St ion implantation layer was replaced with Si3N.
A second insulating film No. 4 is deposited.
Ｓ二３Ｎ４はＳ １Ｈ４−ＮＨ３の反応ガス系を用いて
熱分解法により６５０℃〜７００℃の濁度で成長する。S23N4 is grown at a turbidity of 650°C to 700°C by a thermal decomposition method using a reaction gas system of S1H4-NH3.
Ｓｉ３Ｎ４は熱処理中にＧａもＡｓも通すことはない。Si3N4 does not allow Ga or As to pass through during heat treatment.
次に第２図（ｄ）に示すように、例えば８５０℃、１５
分の条件で第２の熱処理を行々い、Ｓｉイオン注入層２
をｎ形ＧａＡｓ ＧａＡ、ｓ層５に変える。この時ｎ形
ＧａＡｓ層のキャリア濃度は注入されたＳｉがどの程度
活性化しているか、すなわちＳｔがどの位Ｇａサイトを
占めているかに依る。従っ＼
て前述したごとく、前もってＧａの空孔を作っておくこ
とにより注入された８ｉが熱処理中に（）ａサイトラ占
める割合が増すと共に、この割合は主にＧａの空孔の量
に比例すると共にそれにより制御されるので、基板の結
晶性の影響を受けることが少なくなる。本発明の効果は
形成されたｎ形ＧａＡｓ１のキャリア濃度プロファイル
を調べること罠より示すことができる。第３図は、本発
明によるｎ形Ｇ ａ Ａ ｓ層と従来方法によるｎ形Ｇ
ａＡｓ層とのキャリア濃度プロファイルの比較を示した
ものであり、縦軸はキャリア濃度度を横軸は表面からの
深さを示し、破約は注入Ｓｉの濃度分布を示す。Next, as shown in FIG. 2(d), for example, at 850°C, 15
A second heat treatment is performed under the conditions of
is changed to an n-type GaAs GaA, s layer 5. At this time, the carrier concentration of the n-type GaAs layer depends on how much the implanted Si is activated, that is, how many Ga sites are occupied by St. Therefore, as mentioned above, by creating Ga vacancies in advance, the ratio of the injected 8i to the ()a site increases during heat treatment, and this ratio is mainly proportional to the amount of Ga vacancies. Since the crystallinity of the substrate is controlled by this, it is less affected by the crystallinity of the substrate. The effects of the present invention can be demonstrated by examining the carrier concentration profile of the formed n-type GaAs1. FIG. 3 shows an n-type Ga As layer according to the present invention and an n-type Ga As layer according to the conventional method.
It shows a comparison of the carrier concentration profile with the aAs layer, where the vertical axis shows the carrier concentration, the horizontal axis shows the depth from the surface, and the breakdown shows the concentration distribution of implanted Si.
第３図に示すように、５ｉ０２保護膜を用いた従来方法
によるｎ形ＧａＡ、ｓ層のキャリア濃度プロファイルＡ
は、表面側で活性化されておらず、これが熱処理中に多
叶のＧａがＳ ｉ ０２膜を通して抜は出たことによる
結晶性の劣化によるものであることを顕著に示している
。第３図のキャリア濃度プロファイルＢ ｉｄ Ｓ ｉ
３Ｎ ４保護膜を用いた従来方法に上るｎ ＪＵ Ｇ
ａ Ａｓ層のものであり、キャリア６度プロファイルＣ
は注入前に前もってＧａ空孔を形成しておいた本発明（
（なるｎ形ＧａＡｓ、Ｉｔｆ？のものである。第３図に
示すキャリア濃度プロファイルＡ１Ｂ１０から判るよう
に、本発明になるｎ形Ｇ ａ Ａ ｓ層のキャリア旋度
プロファイルは、従来方法のものに比べて、ピークキャ
リア濃度で１〜３倍高くなっておシ、注入されたＳｉが
より多く活性化していることを示している。As shown in Fig. 3, carrier concentration profile A of n-type GaA and s-layers obtained by the conventional method using a 5i02 protective film.
was not activated on the surface side, which clearly indicates that this is due to the deterioration of crystallinity due to the multilayered Ga being extracted through the SiO2 film during heat treatment. Carrier concentration profile B id S i in Figure 3
3N 4 Over conventional method using protective film n JU G
a As layer, carrier 6 degree profile C
In this invention, Ga vacancies were formed in advance before injection (
(N-type GaAs, Itf?) As can be seen from the carrier concentration profiles A1B10 shown in FIG. 3, the carrier rotation profile of the n-type GaAs layer according to the present invention is similar to that of the conventional method. In comparison, the peak carrier concentration was 1 to 3 times higher, indicating that more of the implanted Si was activated.
本発明の考え方は、ＧａＡｓに対してのみならず、イン
ジウムリン等信の化合物半導体に対しても十分に適用可
能なものである。The concept of the present invention is fully applicable not only to GaAs but also to compound semiconductors such as indium phosphide.
また前記一実施例においては、イオン注入した不純物の
活性化のための熱処理を行なうために化合物半導体表面
をシリコンナイトライド膜でａつだ場合について示した
が、このシリコンナイトライド膜は必ずしも必要なく、
直接熱処理を行なういわゆるキャップレスアニールであ
ってもよい。Furthermore, in the above embodiment, a case was shown in which the surface of the compound semiconductor was covered with a silicon nitride film in order to perform heat treatment to activate the ion-implanted impurities, but this silicon nitride film is not necessarily necessary. ,
So-called capless annealing in which direct heat treatment is performed may also be used.
第１図（ａ）〜（Ｃ）は従来方法を説明するだめの図で
第２図（ａ）〜（ｄ）は本発明の一実施例を説明するだ
めの図である。第３図は本発明と従来方法によるｎ形Ｇ
ａ Ａ ｓ層のキャリア濃度プロファイルを示すもの
であり本発明の効果を示す。
１は半絶縁性ＧａＡｓ、２は第１の絶縁膜、３はＳｉ
イオン注入層、４は第２の絶縁膜、５はｎ形Ｇ ａ Ａ
ｓ層、６は保設膜である。1(a) to 1(C) are diagrams for explaining the conventional method, and FIGS. 2(a) to 2(d) are diagrams for explaining one embodiment of the present invention. Figure 3 shows n-type G according to the present invention and the conventional method.
This figure shows the carrier concentration profile of the aAs layer and shows the effects of the present invention. 1 is semi-insulating GaAs, 2 is the first insulating film, 3 is Si
ion implantation layer, 4 a second insulating film, 5 an n-type Ga A
The s-layer 6 is a storage film.
Claims (1)
れを熱処理によって活性化せしめて半導体活性層を形成
する方法において、化合物半導体の一面にシリコンオキ
シナイド膜を被着させて熱処理を行い、前記化合物半導
体基板内にあらかじめ結晶欠陥を形成した後前記不純物
をイオン注入せしめ、これを熱処理によって活性化せし
めることを特徴とする半導体活性層の形成方法。In a method of ion-implanting impurities into a compound semiconductor substrate and then activating it by heat treatment to form a semiconductor active layer, a silicon oxynide film is deposited on one surface of the compound semiconductor, heat treatment is performed, and the compound semiconductor is ion-implanted. 1. A method for forming a semiconductor active layer, which comprises forming crystal defects in a semiconductor substrate in advance, then ion-implanting the impurity, and activating the impurity by heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58147532A JPS6039826A (en) | 1983-08-12 | 1983-08-12 | Formation of semiconductor active layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58147532A JPS6039826A (en) | 1983-08-12 | 1983-08-12 | Formation of semiconductor active layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6039826A true JPS6039826A (en) | 1985-03-01 |
Family
ID=15432436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58147532A Pending JPS6039826A (en) | 1983-08-12 | 1983-08-12 | Formation of semiconductor active layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039826A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57173083U (en) * | 1981-04-24 | 1982-10-30 | ||
| US4713354A (en) * | 1985-02-28 | 1987-12-15 | Oki Electric Industry Co., Ltd. | Method of heat treatment for reduction of dislocation density near III-V substrate surface |
-
1983
- 1983-08-12 JP JP58147532A patent/JPS6039826A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57173083U (en) * | 1981-04-24 | 1982-10-30 | ||
| US4713354A (en) * | 1985-02-28 | 1987-12-15 | Oki Electric Industry Co., Ltd. | Method of heat treatment for reduction of dislocation density near III-V substrate surface |
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