JPS6038903B2 - Multiplex transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for converting a large number of digital parallel input data into serial data and performing multiplex transmission, and particularly to a synchronization system.

The principle of conventional multiplex transmission of a large number of parallel digital data can be explained using the rotary switch model shown in FIG. That is, parallel data is transmitted to terminals 1. , 12, . . . , ln, and is first stored in register 2. The rotary switch 3 rotates and sequentially sweeps the stored contents according to a command from the transmitting side synchronous circuit 4, converts them into serial data, and sends the data to the transmission line 5.

The structure of a general transmission signal, which is serial data sent out to the transmission line 5, is as shown in FIGS. 2 and 3 as an example.
A frame is set up as a large unit, and the frame is divided into several words, and usually 8 to 20 bits are divided into 1 word.
constitutes a word. The serial data is also transmitted by a rotary switch 7 that rotates according to a command from a synchronous circuit 6 on the receiving side.
The data is converted into the original parallel data and stored in the register 8.
Here, in order for the parallel data on the transmitting side to completely correspond to the parallel data on the receiving side, the rotary switch 3 on the transmitting side must
It is necessary that the rotational speed of the rotary switch 7 on the receiving side and the connection position during rotation match, and the synchronous circuits 4 and 6 perform this operation. Synchronizing the rotational speed is called bit synchronization, and synchronizing the connection position is called word synchronization or frame synchronization.

Bit synchronization is the delay included in serial data.

The high-Q resonator is used to extract the high-frequency components.
As shown in Figure 2, frame synchronization involves inserting a frame synchronization signal at the beginning of serial data, searching for this synchronization signal on the receiving side, and confirming that frame synchronization has been achieved when a predetermined pattern is obtained. If a determined pattern cannot be obtained, synchronization is achieved by advancing or delaying the rotation of the rotary switch 7 one step at a time, that is, by shifting one bit at a time.

Furthermore, since the start position can be determined by frame synchronization, the position of the word can be determined by counting the number of bits. In other words, word synchronization can be achieved.

Conventionally, in the frame synchronization pattern, all bits are set to "1" for one word or two words, and then several data words are inserted to form one frame. In this case, if all bits of two consecutive data words happen to be set to "1", the receiving side will not be able to distinguish between a synchronization signal and a data signal, making it difficult to establish frame synchronization. be.

This tendency is particularly noticeable when the parallel data to be transmitted changes slowly.

The present invention has been made in view of the above, and it is an object of the present invention to provide a multiplex transmission system in which synchronization signals can be clearly distinguished for any input data, and synchronization is less likely to occur.

That is, the present invention inserts a frame synchronization signal into every word in a frame, and makes the synchronization signal a different pattern for each word in the frame, thereby reducing the probability that the data pattern and the synchronization pattern will be the same. This is an extremely small amount.

FIG. 3 shows an example of inserting a synchronization pattern in the present invention. One word consists of 10 bits, of which 2 bits are assigned to a synchronization pattern.

Furthermore, one frame is composed of four words. That is, the 2-bit synchronization pattern of each word constituting one frame is "1.0'', "0.1", "1.1", "0.
The frame synchronization is achieved by reading all bits including this signal. FIG. 4 shows the configuration of the transmitter.

1 river clock generator, 11 is decimal counter, 12 is quaternary counter, 13, 14, 15, 16 are 16 → 1 data selector, 17 is 4 → 1 data selector, 18 is PR
OM, 19 is an OR gate.

The output pulses of the clock generator 10 are counted by an IG Hayabusa counter 1 and a quaternary counter 12. The total number of input data is 32 bits, which is divided into four groups, 0th to 3rd. Only one data of the 0th group is selected by the 16→1 data selector 13, and similarly for the 1st to 3rd groups, the 16→1 data selector 14, 1
5 and 16, only one is selected. As the select signal section for this purpose, the lower 4 bits of the counter output To,
T,,T2,T3 are used. The outputs of the 16→1 data selectors 13, 14, 15, and 16 are determined by the 4→1 data selector 17 as to whether or not to output the data of the group 1.

The select signal for this purpose is the upper 2 of the counter output.
Bits L and T5 are used. Counter is 00...0
When counting is performed sequentially, 4→1 data selector 1
Since the select input of 7 is 00, 16 → 1 data selector 1
3 output is selected.

Furthermore, since the lower four bits are also 0, the input Do of the 16→1 data selector 13 is output. Next, the counter is 10
...0, the 16→1 data selector 13 is also selected, and the input D is output. In this way, when the counter reaches 100100, D9 is output. The next count is 000010, and since the select input of the 4→1 data selector 17 is 10, the output of the 16→1 data selector 14 is selected. Similarly, when the last data belonging to the 16→1 data selector 16 is output, the counter returns to 00...0 and repeats the operation from the beginning.

Here, in order to send out the synchronization signal, {1} The contents of the synchronization signal are stored in the PROM 18, and when a predetermined timing comes, the synchronization signal is sent without sending data, and ■ each 16 → 1 data selector 13, 1
4, 15, 16 are the inputs Do, D. should be grounded (
0 output) Allow data to enter D2 to D9 (D,.

~D, 5 is for inconvenience because no select signal is provided). The synchronization signal is sent out in the following manner.

The timing at which the synchronization signal should be sent is when the count number is IG.
"0""1""10""11""20""21" in Hayabusa display
”, “30”, “31”, “000000” and “
○○○○○1” “01000○” “○10001
” “100000” “100001” “1100
00" and "110001" (Displayed in the order of T5 → 9. The upper 2 bits are a binary counter, and the lower 4 bits are 1.
(It is a 0-base counter). To to L are connected to the address input of PORM18, and "0 first place (1 Bo Hayabusa) ... 1 "1 first place (IG Hayabusa) ... 0 "10"〃( 〃 )-- ○ "11"〃(〃)...1 "20"〃(〃). ．．・1 “21”〃( 〃). ...1 "30"〃(〃)...0 "31"〃(〃)...0 are stored, and "0" is stored in all other addresses.

Therefore, the synchronization signal is sent out at the timing when the synchronization signal should be sent out. In addition, 16 → 1 data selector 1
The Do, D inputs of 3, 14, 15, and 16 are grounded, and since these data are output at the above timing, they are always "0", which is the same as no data output.

Data signal output from 4→1 data selector 17 and PR
The synchronization signal output from the OM 18 is combined at an OR gate 19, and both are multiplexed and transmitted into one output without overlapping.

FIG. 5 shows the configuration of the receiving section.

20 is a clock regeneration circuit, 21 is a NAND gate, 22
is a decimal counter, 23 is a quaternary counter, 24 is a PROM
, 25 is a monostable multipipulator, 26 is an exclusive OR
Gate, 27 is NOT gate, 28, 29, 30, 32
is an AND gate, 31 is a flip-flop, 33 is 1→
4 demultiplexer, 34, 35, 36, 37 are 1 → 8
Demultiplexers 38, 39, 40, and 41 are latches.

The input data is clock-regenerated by a resonant circuit or the like in the clock regeneration circuit 20, which passes through the NAND gate 21 and enters the counting input terminals of the counters 22 and 23, and outputs timing signals To to T5 (To is the highest Lower, T
5 is the top rank again). The other input of the NAND gate 21 receives the output of the monostable multi-noise controller 25, and when it is at a high level, the clock is prohibited from inputting to the counter 22, and the counting state is delayed by one count (the reason for this is (described later). The PROM 24 has exactly the same contents as the PROM 18 of the transmitter, the outputs of the counters 22 and 23 are connected to the address input, and the contents are read out at the timing when the synchronization signal is to be output. The input data is input to an exclusive OR gate 26 together with the output of the PROM 24, and if the input signals match, "0" is output, and if they do not match, "1" is output.

The AND gate 29 for creating judgment timing has T, .
T2, T3 (inversion of T,, L, T3), clock (CL
4 signals of K) are input, and the output is the count "〇" and "1".
” “10” “11” “20” “21” “30” “31”
The clock is output only when (IG Hayabusa display). This enters an AND gate (coincidence judgment gate) 28 and an AND gate (mismatch judgment gate) 301. That is, AND
When the gates 28 and 30 go high, a match or mismatch is determined at each gate. The AND gate 29 takes out only consecutive 2-bit clocks every 10 bits.

That is, this timing coincides with the sending timing of the synchronization signal, and is used to determine whether the synchronization signal is indeed received at the timing when the synchronization signal should be received. If the input data matches the output data of the PROM 24 at the above-mentioned judgment timing, a match judgment output is output from the AND gate 28, and the SR flip-flop 31 of the judgment result memory is set.

If the input data and the PROM 24 output do not match at the above-mentioned judgment timing, a mismatch judgment output is output from the AND gate 30, and the SR flip-flop 31 of the judgment result memory is set.

At the same time, the output of the AND gate 30 drives the monostable multipipulator 25, so that the clock does not enter the 1-bit output counter in the NAND gate 21 while the output is output from the monostable multipipulator 25. In this way,
The state of the counter is delayed by one bit relative to the input data. This operation is repeated until there is no non-coincidence determination output. When the non-coincidence determination output is no longer output, it means that the input data and the synchronization signal of the PROM 24 have been completely synchronized. SR flip-flop that stores judgment results.

If the input data and the output of the PROM 24 always match at the above-mentioned timing (if the transmitting side and the receiving side are synchronized), a high level is always outputted to the output of the chip 31. The AND gate 32 prevents input data from being input to the 1→4 demultiplexer 33 when synchronization is incomplete, and input data is input to the 1→4 demultiplexer 33 only when the synchronization judgment result memory output is at a high level. is input.

The signal entering the 1→4 demultiplexer 33 is distributed to four outputs by the counter outputs L and T5, and each output is further distributed to the 1→8 demultiplexer 34, 35, 36, 3.
At 7, the counter outputs L to T3 are respectively 8.
divided into two outputs, latches 38, 39, 40, 4
1 is stored.

In the above embodiment, the synchronization signal bits are 2 bits, but the number is not limited to this.

As the number of bits increases, it becomes easier to identify synchronization signals and the probability of synchronization decreases. As explained above, in the present invention, the synchronization pattern is constantly changing, so even if the synchronization pattern and the data pattern match, it will only be for a moment, and they will not match for a long time. There is no need to worry about getting out of synchronization as in the past. Also, since the information for frame synchronization is distributed in each word within the frame, data "0" and "1"
Even if there is a succession of "0" and "1" in the transmission signal, the succession of "0" and "1" occurs only within a word, which is convenient for bit synchronization (timing extraction).

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of a multiplexed transmission system, Fig. 2 is an explanatory diagram of a conventional multiplexed serial signal, Fig. 3 is an explanatory diagram of an example of a multiplexed serial signal in the present invention, and Fig. 4 is an explanatory diagram of an example of a multiplexed serial signal in the present invention. FIG. 5 is an explanatory diagram of the circuit of the transmitting section. FIG. 5 is an explanatory diagram of the circuit of the receiving section in the present invention. Eagle 1 figure and 2 tooth momme 38 cumulative 4 figure groove S8

Claims (1)

[Claims] 1. In a method that converts parallel data into serial data and performs multiplex transmission, each word in a frame is provided with at least two synchronization bits, and the contents of the synchronization bits are changed for each word, and these synchronization A multiplex transmission method that is characterized by reading all bit contents and achieving frame synchronization based on this reading.