JPS6038799B2 - Non-volatile semiconductor memory circuit - Google Patents

Description

[Detailed Description of the Invention] {1} Technical Field of the Invention The present invention relates to a non-volatile semiconductor memory circuit, particularly an EEPROM.
(Electric Enesable Program
(mableRead-OnlyMemory) circuit.

■Technical Background In recent years, electrically programmable and erasable nonvolatile semiconductor memory circuits have come into widespread use.

This is because there is no inconvenience such as using ultraviolet light. The principle of writing and erasing is the so-called tunnel effect.
This is done by a thin film formed between the floating gate and drain of the MOS transistor that constitutes the memory cell. A control gate coupled to a capacitor is further provided on the floating gate, and by changing the voltage level to be applied to these control gates, drains, etc., write mode, read mode, and erase mode are set. In this case, the threshold level of the MOS transistor also varies depending on the voltage applied to the control gate and drain, that is, the erase voltage and write voltage. This variation should vary within a certain range, which requires some kind of control gate bias circuit during readout. However, this EEP
ROM itself has a short history, and no established bias circuit has been proposed yet. For this reason, the emergence of some kind of bias circuit is awaited with the intention of improving the quality of EEPROMs. {3' Problems with the prior art Considering the above-mentioned background, there is no established prior art, at least regarding the bias circuit.

For this reason, a problem has arisen in that the voltage of the control gate of the memory cell cannot be maintained properly, especially during reading. In principle, the voltage of the control gate at the time of production can be fixed at, for example, V (in other words, no bias), but when considering mass production, it is difficult to keep the voltage of the control gate fixed. It's extremely inconvenient. This is because the thickness of the thin insulating film provided between the floating gate and the drain varies due to manufacturing variations between wafers and within a wafer. Furthermore, the channel length or channel width of the MOS transistor also varies. Furthermore, even after commercialization, it is necessary to plan for fluctuations in power supply voltage. However, in the past, since such fluctuations were not taken into consideration, there remained a problem in that it was difficult to always ensure the control gate voltage during proper discharge. {4) Purpose of the Invention Accordingly, the purpose of the present invention is to propose a non-volatile semiconductor memory circuit in which a stable and appropriate control gate voltage is automatically applied during readout at all times in response to the above-mentioned fluctuations.

Structure of the Invention In order to achieve the above object, the present invention forms on the same chip a group of dummy circuit elements having almost the same configuration as a sense amplifier circuit, a selection transistor for decoding, etc. provided incidentally to a group of memory cells. , the control gate voltage is obtained through the dummy circuit element group during reading.

■ Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a state in which a bias circuit portion according to the present invention is added to a general nonvolatile semiconductor memory circuit. The nonvolatile semiconductor memory circuit 10 includes a bias circuit 11 according to the present invention and a plurality of column selection lines 12i, 12i.
(only two are shown), and multiple row wires 13k, 131 (2
) and multiple bit lines B,,B2,...B,
6, &, . . . B8 is provided. This row wire 13k
, 131 and bit line B. 2nd place at the intersection with...
A memory cell consisting of a bare MOS transistor 14 shown in the figure and a selection transistor 22 for selecting it is provided.

The selection transistor 22 is connected to the row lines 13k, 131 and the bit lines B, . It is connected. This memory cell consists of 8 cells as one unit (lbyte)
The control gates of each unit are column gate transistors 15i, 15j, and control gates.

Column line CGS for gate selection and row control gate selection transistors 6kl, 16k2, 1611
, 1612 to the bias circuit 11. C
L.G.・・・． ...CLG. 8,CLG2,.・・・．
...GLG28 is a column selection transistor, which connects the bit lines Bu...B to the output bus 17 (representing an 8-bit bus).

Then, output bus 17 has a bit-compatible sense amplifier circuit (
18: n is an input section, 18; 18 (only 1 bit out of 8 bits is shown) is provided, and data Dout is read out from the output buffer circuit 19. At the time of writing, the selection transistor 22 of the desired memory cell is turned on,
When the write signal W is applied, the transistor Qw is turned on, and the ground potential OND is applied to the control gate of the specified cell group (every 8 bits) via the selection transistors 15 and 16.
CG.

During erasing, an erase signal E is applied, the transistor QE is turned on, and a voltage Vpp of, for example, 20 V is similarly applied to the control gate CQ of the designated cell group. The present invention particularly refers to the time of reading, and when transistor QB is turned on in response to read signal R (other transistor Q
Both E and Qw are off). FIG. 2 is a sectional view showing the general structure of the MOS transistor 4 shown in FIG.

CG and FG are the control gate and floating gate described above, and are installed on the channel sandwiched between the source S and drain D in the semiconductor substrate 21 with the insulating film 1 interposed therebetween. In the case of deletion, as mentioned above,
A high voltage Vpp (=20V) is applied to the control gate CG, and the drain D is set to the ground potential CND. Then, a high voltage is applied to the floating gate FG by the capacitor coupling between the gates CG and FG, and a high electric field is formed in the very thin insulating film 1' between the gate FG and the drain D. Electrons are injected from the drain D into the floating gate FG due to the tunnel effect, and erasing is completed. On the other hand, during writing, the voltage relationship described above is reversed to reverse the direction of the high electric field applied to the insulating film 1'. Then, the electrons injected into the floating gate FG are extracted, and the data "1" is extracted.
" has been written. If the data is "0", it is sufficient to keep injecting electrons. The above is already known. By the way, in the present invention, the voltage of the control gate CG mentioned above is changed. This refers to how to bias appropriately.

Figure 3 shows erase, write and read states and MOS transistor 1
4 is a graph showing the relationship with the threshold level Vth, and will be explained using this graph. As mentioned above, since the threshold voltage of the MOS transistor 14 of the memory cell is at the points 1 and 2 in this graph due to writing and erasing, the voltage of the control gate at the time of reading must be at the middle point 2 between them. At that time, the threshold level Vw
, VE and the output voltage VR are, for example, Vw=0 to -2V, VR=0.5 to IV, and VE=3 to 5V. The VR at the time of reading is 0.5 to IV, but it varies depending on the various factors mentioned above and is not always maintained properly.

In other words, it often deviates either upward or downward in this graph. This is not preferable for stable and accurate reading. FIG. 4 is a circuit diagram showing a specific example of the bias circuit 11 according to the present invention.

Note that in the past, this type of bias circuit did not exist, and a predetermined fixed level was applied to the transistor QR (see also FIG. 1). The configuration of this bias circuit 11 is as follows:
It consists of a dummy sense amplifier circuit 41, a dummy cell 42, and a voltage setting circuit 43, which have almost the same configuration as the sense up circuit 18 shown in the figure. The dummy cell 42 includes a first transistor 44 having the same configuration as the MOS transistor 4 described above and including a floating gate FG and a control gate CG, and a second transistor 45 having almost the same configuration as the selection transistor 22 of the cell. These series-connected transistors 44 and 45 extract a predetermined current i from the input section 41in of the dummy sense amplifier circuit 41 and guide it to the ground (GND). The magnitude of this current i is always maintained at a constant magnitude. This is the voltage setting circuit 43
The output voltage Vout of transistor 4 is partially branched to
This is because it is fed back to the control gate CG of No. 4. That is, when the current i increases, the output section 41 of the dummy sense amplifier circuit 41. Since the voltage at ut falls and the output voltage V side of the setting circuit 43 also falls, feedback is applied to reduce the current i. Conversely, even when the current i decreases, the opposite feedback as described above is applied and the current i increases. That is, the current i and the voltage V side are balanced in a certain ÷ constant relationship. This means that EEPROM
This means that the control gate voltage during readout does not change due to fluctuations in the reduced voltage during use after commercialization. However, the greatest advantage is that even if there is manufacturing variation during mass production, especially the manufacturing variation of the MOS transistor 4 mentioned above, the control gate voltage will change in accordance with this variation.

The current i and the output section 41 change optimally according to this variation. This output section 41 is created so that a relationship with the voltage of ut is created. Adjust the voltage of ut in advance to find the optimal voltage V.
Must obtain uL. This is the role of the voltage setting circuit 43. Therefore, the dimensions of each element in the circuit 43 are predetermined so that a predetermined V skin is generated. In the end, the load that is exactly the same as the peripheral circuit or peripheral element seen from the MOS transistor 4 in Fig. 1 is built into the same chip in the same process, and the variations are canceled out. , actually generates the voltage applied to the control gate CQ.

Note that instead of a thin film, a cell using a thick film can be used as the dummy cell, with the FG-D capacitance and CG-FG capacitance being made equivalent. However, at this time, the increase in the FG-S intercostal capacity must be kept to a minimum. [7}
Effects of the Invention As explained above, according to the present invention, it is possible to automatically generate an appropriate control gate voltage during readout, adapting to manufacturing variations during mass production and also adapting to power supply voltage fluctuations during use. be.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a general nonvolatile semiconductor memory circuit in which a bias circuit according to the present invention is added, and FIG. 2 is a cross-sectional view showing the general structure of the MOS transistor 4 shown in FIG. 1. , Figure 3 shows the erase/write/read state and the MOS
FIG. 4 is a graph showing the relationship between the threshold level V of the transistor 4 and the bias circuit 11 according to the present invention.
FIG. 2 is a circuit diagram showing a specific example. 11... Bias circuit, 12i, 12j... Column selection line, 13k, 131... Row line, 14... MOS transistor, 15i, 15i... Column gate transistor, 16kl, 16K2, 1611, 1612... Row control gate Selection transistor, 18...Sense amplifier circuit, 41...Dummy sense amplifier circuit, 42...Dummy cell, 43...Voltage setting circuit, 44...First transistor, 45...Second transistor, FG...Floating gate , CG...control gate. Figure 2 Figure 3 Figure 4 Figure 1

Claims (1)

[Claims] 1. A nonvolatile semiconductor memory cell consisting of a plurality of bit lines and a plurality of row lines, and a MOS transistor provided at the intersection of these bit lines and row lines, each of which has a built-in floating gate and a control gate; a bias circuit that applies a read voltage to the control gate of the selected non-volatile semiconductor memory cell; and a bias circuit that receives read data from the selected non-volatile semiconductor memory cell at an input section and amplifies the read data from an output section. A nonvolatile semiconductor memory circuit comprising a sense amplifier circuit for transmitting data, a dummy cell having substantially the same configuration as the nonvolatile semiconductor memory cell, and the sense amplifier for supplying current to the dummy cell and outputting a voltage corresponding to the amount of current. a dummy sense amplifier circuit having substantially the same configuration as the circuit, outputting the read voltage in proportion to the output of the dummy sense amplifier circuit, and applying the read voltage to a control gate in the dummy cell; A nonvolatile semiconductor memory circuit comprising the bias circuit described above.