JPS6038671B2 - Crystal clock with fully automatic speed control circuit - Google Patents

Description

[Detailed description of the invention] TECHNICAL FIELD The present invention relates to rate regulation of a quartz watch.

The present invention provides a configuration for automatically setting the amount of adjustment in a adjustment method that varies the frequency division ratio of a frequency dividing circuit that divides the signal of a crystal oscillator, and furthermore, it provides a configuration for automatically setting the adjustment amount. This provides a configuration to prevent this.

FIG. 1 shows a block diagram of a conventional quartz watch having a fully automatic speed control circuit.

1 is a crystal oscillator, 2 is a frequency dividing circuit, 3 is a display means, 4 is a frequency deviation measuring circuit for measuring the frequency deviation of the oscillation frequency of the crystal oscillator with respect to standard time, and 5 is a frequency deviation measured by the frequency deviation measuring circuit. , or a frequency deviation storage circuit that stores the code-converted frequency deviation; 6 a rate adjustment circuit that controls the frequency division ratio according to the data stored in the frequency deviation storage circuit 5 to adjust the rate; and 7 a clock body; receiving means for receiving a standard time signal input from the outside; 8 a control circuit for controlling each of the circuits and means; 9;
is a speed/speed lock switch for not operating the circuit even if a signal is input to the receiving means 7 when the system is not in the speed/speed state.

When the slow/fast lock switch is rubbed ON', the locked state is released, a reset signal is output from a of the control circuit 8, and the frequency deviation measuring circuit 4 is reset. In this state, the receiving means 7 receives a standard time signal with a time interval of 1 second or 2 seconds from the outside.
When the frequency deviation measurement command signal b is sent, the frequency deviation measurement circuit 4 measures the oscillation frequency of the crystal oscillator that occurs during 1 or 2 seconds of the standard time signal, and measures the frequency deviation with respect to the standard frequency. do. Next, the value of the frequency deviation measurement circuit is written into the frequency deviation storage circuit 5 by the storage command signal c, and the adjustment of speed is completed. Here, by turning off the adjustment lock switch 9, it is possible to avoid setting the adjustment amount due to noise, and the rate adjustment circuit 6 can be adjusted by the amount that matches the data stored in the frequency deviation storage circuit 5.
The rate is adjusted by varying the frequency division ratio. In this manner, in a crystal watch having a fully automatic adjustment circuit, as long as a device for generating a standard time signal is provided, the rate can be adjusted fully automatically by receiving an external standard time signal through simple operations. A detailed explanation of such a configuration is given in Japanese Patent Publication No. 5397, published by the same applicant.
However, by turning off the slow/sudden lock switch 9, incorrect setting of the slow/sudden amount can be avoided during the period when the lock switch 9 is OFF, but when the slow/sudden lock switch 9 is ON, the signal cannot be distinguished from the standard time signal. It is not possible to prevent incorrect setting of the adjustment amount due to noise signals.

An example of a circuit configuration according to the present invention is shown in FIG.

The following explanation will be based on this. 1 is a crystal oscillator,
2 is an abbreviation for frequency division circuit; 3 is a display means; 5 is a frequency deviation storage circuit; 6 is a rate adjustment circuit; 7 is a standard signal receiving means; 8 is a control circuit that controls each of the aforementioned circuits and means; 9 is a adjustment lock. Switches 10 and 11 are D-type master-slave flip-flops, 12 is a write command signal inhibit gate, and 13 is a NOR gate.

In the embodiment shown in FIG. 2, the frequency deviation measuring circuit 4 shown in FIG. 1 is omitted, and a part of the frequency dividing circuit 2, which has no particular role at the time of setting speed and speed, is used as the frequency measuring circuit. still,
It goes without saying that the frequency deviation measuring circuit 4 may be provided separately from the frequency dividing circuit 1 as shown in FIG. When the slow/fast lock switch 9 is turned on, the output of the NOR gate 13 is at low level since the output S2 of the flip-flop 11 is at low level.
The frequency divider circuit 2 (in this case, functions as a deviation measurement counter).

) is in the reset state. When the external standard time signal is input to the receiving means 7 in this state, the output S of the flip-flop 10 becomes high level. The next stage flip-flop 11 is triggered by the output of the oscillator 1, and the output S2
becomes a high level and is input to the NOR gate, so the output of the NOR gate becomes a low level and is input to the frequency divider 2.
The reset of oscillator 1 is released, and measurement of the signal of oscillator 1 by frequency divider circuit 2, which functions as a deviation measurement counter, begins. In this state, when the second external standard time signal is input a certain standard time T after the first signal (usually 1 to 2 seconds later), the output S of flip-flop 1 becomes low level, and the output of flip-flop 11 becomes low level. A write signal is output from the output M of , and the value of the frequency divider circuit 2 at that time is written and stored in the deviation storage circuit 5. The value of frequency divider circuit 2 at this time is standard time T
Corresponding to the oscillation frequency of the oscillator 1 that occurs during this period, the deviation from the normal frequency can be measured. Next, a little later than the output M, S2 becomes low level, and after the writing is completed, the frequency dividing circuit 2
is in a reset state. If a noise signal is input before the second regular standard time signal is input,
It becomes impossible to set the correct speed and speed.
In the present invention, a prohibition gate 12 is provided to prevent deliberate setting. The write signal output from the output M of the flip-flop 11 is input to the inhibit gate 12, and the inhibit gate 1
2, a signal formed by the frequency dividing circuit 2 is also input as an inhibition signal. Therefore, when the write signal 1 is input to the deviation storage circuit 5 and the data is written, the prohibition signal formed by the frequency dividing circuit input to the prohibition gate 12 changes from the low level of the prohibition state to the prohibition release state. Only if you reach a high level. In other words, if the prohibition signal configured by the frequency divider circuit is input to the prohibition gate in accordance with the period T of the standard time signal, the normal 2
If the second signal is erroneously input much earlier than the first signal, the write signal M is prohibited by the prohibition gate group 2 and is not output, so that erroneous setting of the adjustment amount can be prevented. For example, the signal input from the frequency dividing circuit 2 to the inhibition gate 12 is
Public eC, ISeC, 0. If there are three signals with a $eC period, the prohibition signal will be as shown in Figure 3b, and the period will be 1.79 seconds to 2 seconds.
．． The prohibition gate will be opened only for 0 mouse seconds, and if the second signal is not input between 1.79 seconds and 2 seconds after the first external signal is input, the deviation will be stored. It is not input to the circuit 5 as a write command signal. The embodiment according to the present invention shown in FIG. 2 is an example in which the oscillation frequency of the oscillation circuit 1 is adjusted in the delay direction and in the advance direction, but even when the oscillation frequency is in the advance direction, the downstream stage of the frequency dividing circuit 2 By adding 1 bit to the signal to form a signal, it becomes possible to similarly pass a signal input within the time period from standard time T to T+Q.

The timing chart of FIG. 2 is shown in FIGS. 3a and 3b.

At the rising edge of the output of the inhibit gate 12, the data of the frequency divider 2 is written into the deviation storage circuit 5. As described above, in the present invention, by providing a prohibition gate and inputting a prohibition signal formed by a frequency dividing circuit to the prohibition gate, the write signal generated by the second signal of the external standard time signal is transmitted for a predetermined period of time. Therefore, even if noise is input when the speed/speed setting is enabled, the speed/speed setting can be prevented from being set incorrectly.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a quartz watch having a fully automatic adjustment circuit. FIG. 2 is a circuit block diagram of a quartz watch having a fully automatic speed control circuit provided with a standard signal prohibition section according to the present invention. FIGS. 3a and 3b are timing charts in FIG. 2. -1... Crystal oscillator, 2... Frequency dividing circuit, 3... Display means, 4... Frequency deviation measurement circuit, 5......・Frequency deviation memory circuit, 6
. . . Rate line express circuit, T . . . Receiving means for receiving a standard time signal, 8 . . . Control circuit, 9 . . .
・・・Rapid lock switch, 10, 11...D
Type master-slave flip-flop, 12...
...Write command signal inhibition gate, 13...NO
R gate. Geno Kyouryo 2 Dan O 3 Diagram

Claims (1)

[Claims] 1 Crystal oscillators, electronic circuits including frequency dividing circuits, display means,
A receiving means for receiving an external signal, a frequency deviation measuring circuit for measuring a frequency deviation of a crystal oscillator with respect to an external standard time signal received by the receiving means, and a frequency deviation measuring circuit for storing the frequency deviation measured by the frequency deviation measuring circuit based on a write signal. It is composed of a frequency deviation storage circuit, a rate adjustment circuit that adjusts the rate according to the frequency division ratio determined by the data in the frequency deviation storage circuit, and a control circuit that controls the adjustment amount setting, and the control circuit receives the external standard time signal. and a flip-flop that starts measurement in the frequency deviation measuring circuit using the first external standard time signal and generates the write signal according to the second external standard time signal, and an inhibit gate circuit that prohibits the write signal. have,
The prohibition gate circuit is characterized in that an prohibition signal for opening the gate only for a predetermined period corresponding to the generation time of the second input signal and allowing the write signal to pass is inputted from the frequency dividing circuit. A crystal clock with an automatic speed control circuit.