JPS6037880A - Binary coding circuit - Google Patents

Abstract

PURPOSE:To obtain an accurate image both in bold line parts and fine line parts by syntherizing and processing signals of reference voltage or less obtained from picture signals and effective signals even above reference voltage. CONSTITUTION:A picture signal 3 is supplied to a comparator circuit 1, a white ground area setting circuit 6 and a minimum value detecting circuit 10. The circuit 1 compares a fixed reference voltage 2 and the signal 3 and outputs a binary picture signal 4. The circuit 6 compares a fixed reference voltage 7 higher than the voltage 2 and the signal 3 and outputs a binary signal 8. The circuit 10 detects an effective signal 15 of voltage 2 or more from signals 3, 4, 8. The signals 4 and 15 are added in an OR circuit 5 to obtain a signal 16. A threshold value processing circuit 9 converts the signal 16 to a signal 18 which is continuous in the picture area. By detecting the effective signals which are not seen in the case of the voltage 2 only, an image of fine line parts becomes accurate.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a binarization circuit, and more particularly to a binarization circuit that converts an analog video signal obtained by scanning an image on microfilm or the like into a binary signal.

(Prior Art) Devices that use optical means and photoelectric conversion means to obtain an image from an image of a document are widely known. The obtained light is imaged on the light-receiving surface of a photoelectric conversion device such as a CCD image sensor, and this is photoelectrically converted.The analog signal obtained by the photoelectric conversion is further converted into a binary video signal, and this binary image signal is converted into a binary video signal. There are devices that obtain images based on video signals.

Conventionally, when converting an analog signal into a 2-sen video signal (hereinafter referred to as an image signal) in this way, generally a reference comparison level is set in advance.
The 2 (JI) conversion circuit was powerfully constructed so that the analog word output obtained by photoelectric conversion was binarized by comparing it with this comparison level, for example, the slice level.

However, with such a conventional binarization circuit, for the reasons described below, it is not possible to obtain a binarized image signal for obtaining an accurate center image.

That is, for example, when a CCD image sensor is used as a photoelectric conversion device, if l/) and l/'1, then the CCD
The amount of light received by the image sensor is determined by the product of the amount of light and the time that the light source illuminates, but since the light source irradiation time ζ is generally constant, the amount of light received is proportional to the amount of light.

Therefore, in the case of a positive microfilm, the amount of light that passes through the thick line portion is small (\), so the amount of light received by the CCD image sensor is small, and the analog image signal that is photoelectrically converted and output from the CCD image sensor is The level is low in the thick line part.Furthermore, since the amount of light passing through the thin line part is large, the amount of light received increases.
The analog image signal has a higher level in the thin line portion than in the thick line portion.

Now, for example, if you set the slice level to a level that allows you to reliably detect thin line areas, the thin line areas will be binarized properly (+ti), but the thick line areas will tend to be thick (thick) in general in the copied image. Since the characters are binarized, the font becomes difficult to read, for example, in the case of characters with a large number of pixels.

Contrary to the above, if the slice level is set to a proper value in the thick line part, this part of the obtained copy image will become blurred or disappear in the thin line part. In other words, the setting standard level may be too low for the thick line part, or too high for the thin line part, and the setting standard level may be too low for the thick line part. It has been extremely difficult to generate a binary image signal from which an image can be obtained.

(Objective) The object of the present invention is to eliminate the above-mentioned drawbacks and to make it possible to supply a binary image signal that allows accurate images to be obtained in both the thick line part and the thin line part of one image. An object of the present invention is to provide a binarization circuit.

More specifically, an object of the present invention is to focus on the particle nature of images on a film as a document, which are formed by the size and density of particles, and to analyze the amount of light received by the image sensor and the density of the particles. Based on the fact that the output analog image signal is obtained in response to the graininess of the output analog image signal,
Detect the minimum value of the image signal that is judged to be valid from among the two, and on the other hand, compare the analog image signal with the slice level to obtain a binary image signal, and obtain, for example, the logical sum of the outputs of both. An object of the present invention is to provide a binarization circuit in which a logical operation is performed in the row l/), and a binary image signal as an output of the logical operation is further processed by a threshold processing circuit.

(Example) The present invention will be described in detail below based on the drawings.

FIG. 1 shows an embodiment of the invention. Here, 1 is a comparison circuit, and the comparison circuit 1 has a fixed reference voltage (slice level) 2 for comparison, which serves as a temporary image area.
An analog image signal output from a CCD image sensor (not shown) is A/D converted to provide an image signal 3 which is an N-bit parallel signal, and a binary image signal 4 obtained by a comparison circuit 1 is converted into a logic signal. It is supplied to the sum circuit 5.

Reference numeral 6 denotes a white background area setting circuit, and the white background area setting circuit 6 is supplied with a fixed reference voltage 7 for setting a white background area corresponding to the background of the document and an image signal 3, thereby setting the white background area to a low level. A binary signal 8 indicated by (L) is generated.

The generated binary signal 8 is further supplied to a negative peak value detection circuit 10 and a threshold value processing circuit 9.

Figure 2 (A) to Figure 2 (11) are
It shows an example of the timing and waveform of the generation of the value image signal 4 and the binary signal 8 for setting the white background area.
A) shows a white area through which light passes and an image area through which no light passes during one scan of microfilm 7.

Here, the shaded area is the image area 20, and 3θ is the white background area. Furthermore, within the image area 20, 2OA or the thick line part, 2
0B is a thin line part. When such a part is scanned in the direction of the arrow with a width 31 as shown in FIG. 2(A),
The image signal 3 from the COD image sensor has a waveform (shown in analog form in this figure) as shown in Figure 2 CB).
occurs, so the comparator circuit 1 to which the slice level 2 is input outputs a binary image signal 4 as shown in FIG. 2(C).

Returning again to FIG. 1, the minimum value detection circuit 10 will be explained. The minimum value detection circuit 10 detects the waveform limited between the slice level 2 in FIG. 2(B) and the white area setting reference voltage 7, that is, the portion corresponding to the thin line portion 20B in FIG. 2(A). This circuit detects the minimum value in the image signal 3.

FIG. 3 shows an example of the minimum value detection circuit 10, where 10
1 and 102 are latch circuits that latch the image signal 3, and the outputs from the latch circuit 101 and the latch circuit 102 are compared in a digital comparator 103.

Here, the parallel signal indicating the digital value generated from the latch circuit 101 and the parallel signal indicating the digital value generated from the latch circuit 102 are compared, and if the signal generated earlier is larger than the subsequent signal, then The comparator 103 generates an output signal "i", and if the previous signal is smaller than the subsequent signal, it generates an output signal '°0'. This is the clock pulse signal supplied to the

FIG. 2(E) shows the output signal 11 generated by the comparator 103 in this manner. By supplying the output signal It to the edge detection circuit 104, the edge detection circuit 104 detects the falling edge of the output signal 11. Detect local minimum values using edges. FIG. 2(F) shows the minimum value detection signal 12, and this minimum value detection signal 12 is connected to the AND gate 105.
supply to.

Furthermore, in FIG. 3, 106 is an AND gate, and the binary image signal 4 is input to the AND gate 106.
A signal 13 inverted by 07 (see FIG. 2 (G)),
The area signal 8 shown in FIG. 2(D) is supplied. As a result, an AND output signal 14 as shown in FIG. 2(H) is output from the AND gate 06.

That is, in Antogame 1/105, the minimum value detection signal 1
2 and the AND output signal 14, a minimum value detection signal 15 in the eye field region as shown in FIG. 2(I) is generated. By supplying this minimum value detection signal 15 to the OR gate 5 as shown in FIG. 1, the OR gate 5 generates an OR output signal as shown in FIG. 16 is generated.

As described above, the minimum value in the image signal effective area indicated by the output signal ゛1''' in FIG. 2(D) was detected by the minimum value detection circuit 10. A continuous output signal °"1" is not obtained in the thin line portion 20B shown in FIG. is necessary.

Therefore, in FIG. 1, a threshold value processing circuit 9 is provided to perform threshold value processing on the output signal 16 to determine an effective image signal area. An example of the circuit configuration is shown in FIG. Here, 8
1 is a bit addition circuit, and the bit addition circuit 81 is supplied with a clock pulse CP, bits (an area discrimination signal 8 for limiting the 1 addition range, and an output signal 16).

Furthermore, 82 is a setting circuit for the Pip) (=J addend, and for the output signal 16, each minimum value output signal °゛1
A focus number K is set in advance, which indicates how many bits can be added to both sides of ``1'' to obtain a continuous output signal ``1''.

Although not shown, the bit addition circuit 91 and bit addition zero number setting circuit 82 can be constructed by combining a shift register and a gate circuit to enable parallel input of loads, for example. can. 16, i.e., the output signal 16
When the information stored in the register is "o" in all digits, the output signal 16 is
A bit signal "1" can be added to both sides of the signal "l".

Fig. 2 (K) shows the binary signal 1 of the continuous output signal °゛1°'' obtained in this way in the image signal effective area.
7 is shown, but it is an extra binary signal that is to be inserted into the signal 17 for each bit at both ends of the output signal "i" of the binary signal 17, and this is deleted. There is a need to.

In FIG. 4, 83 is a bit deletion circuit provided for this purpose, and the bit deletion circuit 93 can be constituted by a combination of, for example, an 8-digit shift register and a logic circuit (not shown).

That is, among the information of the binary signal 17 that is sequentially stored in the shift register from the bit addition circuit 81, only the information stored in the first digit is '0'', or the information stored in the last digit is '0''. When only is "o", all the information stored in the shift register is changed to °°O.
", from the threshold processing circuit 83 to 112
As shown in Figure (L), a correct binary image signal 18 can be generated.

(Effects) As explained above, according to the present invention, for example, an analog image signal from an image sensor is compared with a reference voltage to generate a binary image signal, and in the above-mentioned image area,
An image signal that is determined to be valid from an analog image signal having a reference voltage or higher is detected as a minimum value detection signal, and a binary image signal corrected by, for example, the logical sum of the binary image signal and the minimum value detection signal is formed from the above-mentioned binary image signal and minimum value detection signal. However, since the above-mentioned binary image signal is subjected to threshold value processing using this corrected binary image signal to form a continuous image signal in the image area, it is possible to perform accurate processing even in the thin line part of the image as well as in the thick line part. A binary image signal from which an image can be obtained can be generated.

The present invention is not limited to the case of such transmitted light, but is generally applicable to cases in which reflected light is received by a photoelectric conversion element such as a CCD image sensor and converted into electricity, as in a copying machine or a facsimile machine. Needless to say, it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of the binarization circuit of the present invention, FIG. Figures (Japanese) to Figure 2 (A) are signal waveform diagrams of output signals supplied to each circuit constituting the binarization circuit of the present invention and output signals generated from each circuit, and Figures 3 and 4 are diagrams of the present invention. They are block diagrams each showing an example of the configuration of a minimum value detection circuit and a threshold processing circuit in the binarization circuit of the invention. ■... Comparison circuit, 2... Fixed reference voltage, 3... Image signal, 4. ... Binary image signal 5... OR gate, 6... White background area setting circuit, 7... Fixed reference voltage, 8... Binary signal, 9... Threshold processing circuit, 10... Minimum Value detection circuit, 11-18... Output signal, 20... Light transmission area, 2OA... Thick line part, 20B... Thin line part, 30... White background area, 91... Bit addition circuit, 92... Bit addend setting circuit, 93... Bit deletion circuit, 101.102... Latch circuit, 103... Digital comparator, 104... Edge detection circuit, 105... AND gate, 106...antogame-1., 107...in/<-ri, K...number of hits. Ward Ward Ward Ward Ward C%3 to ~ ~ 0] Hel [Heel Helm Helmet -Q Work -tsu Y ) 9 ++/ +++ 15. Q 9 Ward Ward Ward
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Claims (1)

[Scope of Claims] 1) A first means for generating a binary image signal by comparing an image signal obtained from an image region with a base voltage; a second means for detecting the image signal determined to be valid; and a second means for detecting the image signal determined to be valid;
2, characterized in that it comprises a third means for obtaining a value image signal, and a fourth means for processing the binary image signal with the corrected binary image signal to form a continuous image signal in the image area. I1a conversion circuit. 2. In the binarization circuit according to claim 1, the second means is means for detecting the image signal determined to be valid as a minimum value signal, and the third means: A binarization circuit characterized in that it is means for outputting a logical sum of the binary image signal and the image signal determined to be valid.