JPS6037879A - Binary coding circuit - Google Patents

Abstract

PURPOSE:To obtain an accurate image both in bold line parts and fine line parts of a picture by synthesizing signals of reference voltage or more obtained from picture signals and effective signals even if lower than reference voltage and processing said signals. CONSTITUTION:A picture signal 3 is supplied to a comparator circuit 1, a white ground area setting circuit 6 and a peak value detecting circuit 10. The circuit 1 compares a fixed reference voltage 2 and the signal 3 and outputs a binary picture signal 4. The circuit 6 compares a fixed reference voltage 7 which is lower than the voltage 2 and the singal 3, and outputs a binary signal 8. The circuit 10 detects an effective signal 15 of voltage 2 or less from signals 3, 4, 8. The signals 4 and 15 are added in an OR circuit 5 and a signal 16 is obtained. A threshold value processing circuit 9 converts the signal 16 to a signal 18 which is continuous in the picture area by using the signal 8. By detecting effective signal disappearing under the voltage 2 only, an image of fine line parts becomes accurate.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a binarization circuit, and more particularly to a binarization circuit that converts an analog video signal obtained by scanning an image on microfilm or the like into a binary signal.

(Prior Art) Devices that use optical means and photoelectric conversion means to obtain an image from an image of a document are widely known.
The transmitted light is imaged on the light receiving surface of a photoelectric conversion device such as a CCD image sensor, photoelectrically converted, and the analog signal obtained by the photoelectric conversion is converted into a binary video signal. There is a system that obtains a video based on this binary video signal.

Conventionally, when converting an analog signal into a binary video signal (hereinafter referred to as an image signal), a reference comparison level is generally set in advance, and the analog signal obtained by photoelectric conversion is The binarization circuit was configured to binarize the signal by comparing it with this comparison level, for example, the slice level.

However, in such conventional binarization circuits, it is difficult to obtain accurate images due to the following reasons.
Valued image signal cannot be obtained.

In other words, for example, when a CCD image sensor is used as a photoelectric conversion device, the amount of light received by the CCD image sensor is determined by the product of the amount of light and the light source irradiation time, but since the light source irradiation time is generally constant, the amount of light received is Proportional to the amount of light.

Therefore, in the case of negative microfilm, the amount of light that passes through the thick line area is large, so the amount of light received by the CCD image sensor is large, and the analog image signal that is photoelectrically converted and output from the CCD image sensor is transferred to the thick line area. will be at a high level. Furthermore, since the amount of light passing through the thin line portion is small, the amount of light received is small, and the analog image signal is at a lower level in the thin line portion than in the thick line portion.

For example, if you set the slice level to a level that allows you to reliably detect thin line areas, the thin line areas will be binarized to appropriate values, but the thick line areas will tend to become thicker in the copied image. For example, in the case of characters with a large number of pixels, the font becomes difficult to read.

Contrary to the above, if the slice level is set to a proper value in the thick line part, this part of the obtained copy image will become blurred or disappear in the thin line part. In other words, the set reference level may be too low for the thick line part or too high for the thin line part, making it difficult to obtain an appropriate image for both the thin line part and the thick line part. It was difficult to generate a binary image signal that would

(Objective) The object of the present invention is to eliminate the drawbacks mentioned above and to provide a binary image signal that allows accurate images to be obtained in both thick and thin line parts of the image. The object of the present invention is to provide a binarization circuit with the following characteristics.

Kotoriko Uchi 1. The purpose of this invention is to focus on the particle nature of images on a film as a manuscript, which is formed by the size and density of particles, and to focus on the amount of light received by the image sensor and the amount of light output from the image sensor. Based on the fact that the analog image signal is obtained in accordance with this graininess, the peak value of the image signal that is judged to be effective from among the slice level and below in the analog image signal is detected, and the analog image signal is set to the slice level. By comparing the binary image signal (It), a logical operation such as obtaining the output of both of them, for example, a logical sum, is performed, and the binary image signal as the output of the logical operation is further processed by a threshold processing circuit. The objective is to provide a value converting circuit.

(Example) The present invention will be explained in detail below based on one drawing.

FIG. 1 shows an embodiment of the invention. Here, l is a comparison circuit, and the comparison circuit 1 has a fixed reference voltage (slice level) 2 for comparison, which is used to set a certain image area, and (
Ic: An image obtained by A/D converting an analog image signal output from a D image sensor (not shown) into an N-bit parallel signal (delta No. 3), and a 24fX image obtained by a comparison circuit 1. The signal 4 is supplied to the OR circuit 5.

Reference numeral 6 denotes a white background area setting circuit, and the white background area setting circuit 6 is supplied with a fixed reference voltage 7 and an image signal 3 for setting a white background area corresponding to the background of the document, so that the white background area can be set here. A binary signal 8 indicating a low level (L) is generated. The generated binary signal 8 is further supplied to a peak value detection circuit 10 and a threshold value processing circuit 9.

FIG. 2(A) to FIG. 2(II) are shown in FIG.
It shows an example of the timing and waveforms at which the value image signal 4 and the binary signal 8 for setting the white background area are generated.
A) shows a light transmitting area and a white background area through which no light transmits during one scan on the microfilm.

Here, the shaded area is the light transmitting area 20, and 30 is the white background area. Furthermore, within the light transmitting region 20, 2OA is a thick line portion, and 20B is a thin line portion. This part is shown in Figure 2 (
When scanning in the direction of the arrow with a width 31 as shown in A), an image signal 3 with a waveform (displayed in analog form in this figure) as shown in Fig. 2(B) is output from the COD image sensor. 2 (IM
Image signal 4 is output.

On the other hand, in the white background area setting circuit 6 shown in FIG. From this, a signal 8 for discriminating between a binary white background area and an image signal valid area as shown in FIG. 2(D) is obtained.

Returning to FIG. 1 again, the peak value detection circuit 10 will be explained. The peak value detection circuit 10 detects a waveform limited between the slice level 2 in FIG. 2(B) and the white area setting reference voltage 7, that is, the thin line portion 20 in FIG. 2(A).
This circuit detects the peak value in the image signal 3 of the portion corresponding to B.

FIG. 3 shows an example of the peak value detection circuit lO, where 1
01 and 102 are latch circuits that control the image signal 3;
The outputs from 2 are compared in a digital converter 103. Here, the parallel signal 1 indicating the digital value generated from the launch circuit 101) is compared with the parallel signal Q4g indicating the digital value generated from the launch circuit 102, and the signal generated earlier ( If the i signal is smaller than the i a signal of U6, then the coni rake 103 force) will generate the li lJj chi single signal °'1"°, and if it is larger than the previous signal or the following 4g signal, the output signal '° 0'' is generated. In addition, here, the CP is inserted, the child circuits 101 and 102, and the engineering/engine inspection i.
ll.

This is clock number 11748 supplied to circuit 104.

FIG. 2(E) shows the output signal 11 generated by the converter 103 in this way, and the output signal -11 is processed.

By supplying the signal to the edge detection circuit 104, the edge detection circuit 104 detects a positive peak value based on the edge of the fall 1 of the output signal 11. The 21st N(F)If indicates the peak value detection signal 12, and this peak value direct conversion 133
(8 Furthermore, in FIG. 3, 106 is an AND gate, and the AND gate 106 has 2 (if4 image signal 4 input - signal 13 inverted by 107 (FIG. 2 (G)).
) and the area signal 8 shown in FIG. 2(D). As a result, from ANDK 1-10ft, 21A
Ant output signal 14 as shown in ()I) is output.

That is, in Antogame 1/105, the peak detection signal 1
2 and the AND output signal 14, a peak value detection signal 15 in the limit region as shown in FIG. 2(1) is generated. This peak value detection signal 15 is
By supplying the OR gate 5 as shown in the figure,
The OR gate 5 generates an off output signal 16 as shown in FIG. 2(j) based on the binary image signal 4 from the comparison circuit 1.

As described above, the peak value detection circuit 10 detects the peak (fft) of the IF in the image signal valid region indicated by the output No. 44 "1P" in FIG. 2(D). , No. 1 No. 16 shows f as shown in Fig. 2 (A)
- KQ in Senkyoro 20B
1'' has not been obtained, and a continuous output signal ``1'' is required to determine that this entire range is a valid image signal area.

Therefore, in FIG. 1, a threshold value processing circuit 9 is provided to perform threshold value processing on the output signal 16 to determine an effective image signal area. An example of the circuit configuration is shown in FIG. Here, 8
1 is a bit deletion circuit, and the bit addition circuit 91 is supplied with a clock pulse CP, an area determination signal 8 for limiting the bit addition range, and an output signal 18.

Furthermore, 92 is a setting circuit for the number of bits to be added, and for the output signal 16, each peak value output signal °゛l'' is set.
The number of bits K is set in advance to determine how many bits should be added to both sides of .degree. to obtain a continuous output signal "l.degree.".

Although not shown, the bit addition circuit 81 and the bit addition number setting circuit 92 can be configured by combining a gate circuit and a shift register with a large number of digits that can input loads in parallel, for example. That is, the information stored in the register by the output signal 16 is '0' in all digits.
By changing all the digit information to l°" through the gate circuit when the output signal 16 is ゛'
It is possible to add a bit signal '°1''° (d) to both sides of 1''.

FIG. 2(K) shows the continuous output signal ゛′1°° binary number 1 obtained in this way in the image signal effective area.
7 is shown, but it is an extra binary signal that is to be inserted into the signal 17 for each bit at both ends of the output signal "i" of the binary numbered number 17, and this is Need to be deleted.

In FIG. 4, reference numeral 83 denotes a bit deletion circuit provided for this purpose, and the bit deletion circuit 83 can be constituted by a combination of, for example, an N-digit shift register and a logic circuit (not shown).

That is, among the information with binary numbers 17 stored in the shift register sequentially from the bit addition circuit 91, only the information stored in the first digit is "0°" or R
When the only information stored in the path is "o", all the information stored in the shift register is
By changing to 0, the second
As shown in Figure (L), a correct binary image signal 18 can be generated.

(Effects) As explained above, according to the present invention, for example, an analog image signal from an image sensor is compared with a reference voltage to generate a binary image signal, and in the above-mentioned image area,
An image signal that is determined to be valid from an analog image signal that is lower than a reference voltage is detected as a maximum (iN detection signal), and a binary image signal that is corrected from the above-mentioned binary image signal and local maximum value detection signal, for example, as a logical sum thereof, is Form this correction 2
The above-mentioned binary image signal is subjected to dark value processing using the value image signal,
Since a continuous image signal is formed in the image area, it is possible to generate a binary image signal that provides an accurate image in the thin line portion of the image as well as in the thick line portion.

Note that the above explanation is not limited to cases in which transmitted light is used, such as when using a microfilm, but is generally applied to cases in which reflected light is converted into light by a COD image sensor, etc., such as in a copying machine or facsimile. Needless to say, it can also be used when the element receives light and performs photoelectric conversion.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the configuration of the second imaging circuit of the present invention, Fig. 2 (A) is a model diagram showing a light transmission area in one scanning range on a microfilm, that is, an image area. (B) to (L) are signal waveform diagrams of the output signals supplied to each circuit constituting the binarization circuit of the present invention and the output signals generated from each circuit. FIG. 2 is a block diagram showing an example of the configuration of a peak-to-peak detection circuit and a threshold processing circuit in the binarization circuit of the invention. DESCRIPTION OF SYMBOLS 1... Comparison circuit, 2... Fixed reference voltage, 3... Image signal, 4... Binary image signal, 5... OR gate, 6... White background area setting circuit, 7... Fixed reference voltage, 8...2 signal signals. 9...Threshold processing circuit, 10...Peak value detection circuit, 11-18...Output signal, 20...Light transmission area, 2OA...Bold line part. 20B...thin line part, 30...white background area, 81...bit addition circuit, 92...bit addition number setting circuit, 93...beep) deletion circuit, 101.102...latch Circuit, 103... Digital comparator, 104... Edge detection circuit, 105... AND gate, 106... AND gate, 107... In/beta, K... Number of bits. Patent Applicant Canon Co., Ltd. ward ``'' ward ward ward C%3

Claims (1)

[Scope of Claims] 1) A first means for generating a binary image signal by comparing an image signal obtained from an image area with a reference voltage; a second means for detecting the image signal to be determined; and a second means for correcting the image signal from the binary image signal and the image signal determined to be valid.
2, characterized in that it comprises a third means for obtaining a value image signal, and a fourth means for processing the binary image signal with the corrected binary image signal to form a continuous image signal in the image area. Value circuit. 2. In the binarization circuit according to claim 1, the second means is means for detecting the image signal determined to be valid as a maximum value signal, and the third means is 111. A binarization circuit characterized in that the circuit is a means for outputting a logical sum of the binary image signal described in No. 111 and the image signal determined to be valid. (Hereafter, margin)