JPS6037848A - Bypass type digital multiplex signal converter - Google Patents
Bypass type digital multiplex signal converterInfo
- Publication number
- JPS6037848A JPS6037848A JP14551483A JP14551483A JPS6037848A JP S6037848 A JPS6037848 A JP S6037848A JP 14551483 A JP14551483 A JP 14551483A JP 14551483 A JP14551483 A JP 14551483A JP S6037848 A JPS6037848 A JP S6037848A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- multiplex
- primary
- multiplex signal
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 11
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 230000011664 signaling Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 230000005236 sound signal Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）発明の技術分野
本発明はＤ Ｓ Ｔ （Ｄｉｇｉｔａｌ ５ｐｅｅｃｂ
Ｉｎｔｅｒｐｏｌａｔｉｏｎ）やＬ ＲＥ （Ｌｏｗ
Ｒａｔｅ Ｅｎｃｏｄｅｒ）のシステムなどで用いら
れるデジタル多重信号変換装置に係り、特に信号変換装
置の多重化部の障害時に最小限の回線値保のできるフレ
ーム同期パルスの構成と装置の回路構成に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention relates to
Interpolation) and L RE (Low
The present invention relates to a digital multiplex signal conversion device used in a system such as a rate encoder (Rate Encoder), and in particular to a frame synchronization pulse configuration and a device circuit configuration that can maintain the minimum line value in the event of a failure in the multiplexing section of the signal conversion device.
（ｂ）従来技術と問題力
最近、通話音声信号の冗長性を利用して伝送帯域の圧縮
を行い多重信号の中ｆホ回線の使用りＪ率を上げるため
例えば音声通話路２４個を多重伝送するＰＣＭ−２４方
式の一次群信号（符号速度１．５４４ Ｍ ｂ ／ ｓ
）複数個を一次側入力としこれを同じ速度１．５４４
．Ｍｂ／ｓの二次側多重信号用カー個に帯域圧縮し信号
変換するデジタル多重信号変換装置が考えられている。(b) Prior Art and Problems Recently, the redundancy of speech voice signals has been utilized to compress the transmission band, and in order to increase the usage rate of the f-line among multiplexed signals, for example, 24 voice communication paths have been multiplexed and transmitted. PCM-24 system primary group signal (code rate 1.544 Mb/s
) with multiple inputs as primary side input and the same speed 1.544
．． A digital multiplex signal converter that performs band compression and signal conversion into Mb/s secondary side multiplex signals has been considered.
これらの多重信号変換装置においては、−次回多重信号
と二次側多重信号が同一速度でも二次側信号のフレーム
同期パルスの構成は帯域圧縮後のヒント並びにそれに適
したフレーム構成をとるためまた制御信号の伝送のため
一次側信号とは別の（ｔ￥成のフレーム同期パルスとな
り、二次＋１’ｌ Ｉｎ ”Ｅを伝送する中継装置は一
次側多重信号をそのまま１云送できない構成になること
が多い。そのため多重信号変換装置の多重変換部の障害
時には全回線がｌ：ｌＪｉになるという欠点があった。In these multiplex signal converters, even if the next multiplex signal and the secondary side multiplex signal have the same speed, the configuration of the frame synchronization pulse of the secondary side signal is controlled based on the hint after band compression and the appropriate frame configuration. For signal transmission, the frame synchronization pulse is different from the primary signal (t\), and the relay device that transmits the secondary +1'l In "E has a configuration that cannot transmit the primary side multiplexed signal as it is. Therefore, when there is a failure in the multiplex converter of the multiplex signal converter, there is a drawback that all lines become l:lJi.
（ｃ）発明の目的
本発明の目的は上記の欠点をなくし、多重ｆ＋ｉ ”Ｅ
変換装置の多重変換部が障害を起こしても最小限の回線
が確保されるようなフレーム同期パルスの構成とスイッ
チ回路の構成とを提供することにある。(c) Object of the invention The object of the invention is to eliminate the above-mentioned drawbacks and to
It is an object of the present invention to provide a frame synchronization pulse configuration and a switch circuit configuration that ensure a minimum number of lines even if a multiplex conversion unit of a conversion device fails.
（ｄ）発明の構成
本発明では、二次側多重信号のフレーム同期パルスの構
成を一次側多重信号のフレーム同期パルスを含む構成と
し、装置の一次側入力回線の一つを二次側出力回線に直
結するスイッチ回路を具備する構成とする。(d) Structure of the Invention In the present invention, the frame synchronization pulse of the secondary side multiplexed signal is configured to include the frame synchronization pulse of the primary side multiplexed signal, and one of the primary side input lines of the device is connected to the secondary side output line. The configuration includes a switch circuit directly connected to the
（ｅ）発明の実施例
本発明による実施例を図を用いて説明する。第１図はデ
ジタル多重信号変換伝送方式のブロック図で１は多重信
号変換装置、２ば一次側回線、３は二次側回線、４は中
継装置、Ｓ ａ −、Ｓ ｂはバイパススイッチである
。第２図は多重信号の符号構成図で（８１は一次側信号
、（ｂｌ （Ｃ１は二次側信号の構成例を示す。ｆａｌ
の一次信号はＰＣＭ−２４標準方式の一次群信号を示す
もので１音声信号を８ビツト、８ ｋ ｌｌｚサンプリ
ングの５４ ｋ ｂ ／ ｓで符号化したディジタル音
声信号２４個を時間的に直列に多重化し、２４個の音声
信号毎に１１１１ｉ１のフレーム同期パルスＦ ヲ（ｔ
加り、、た１フレーム１９３個のパルス、符号速度１
、 ５４４Ｍｂ ／ ｓの多重信号であり。(e) Embodiments of the Invention Examples of the present invention will be described with reference to the drawings. Figure 1 is a block diagram of the digital multiplex signal conversion transmission system, where 1 is a multiplex signal conversion device, 2 is a primary line, 3 is a secondary line, 4 is a relay device, and S a -, S b are bypass switches. . FIG. 2 is a code configuration diagram of a multiplexed signal (81 is a primary side signal, (bl (C1 is an example of the configuration of a secondary side signal. fal
The primary signal indicates the primary group signal of the PCM-24 standard system, in which 24 digital audio signals encoded at 54 kb/s with 8 bits and 8 kllz sampling are serially multiplexed in time. 1111i1 frame synchronization pulse F wo(t
193 pulses per frame, code rate 1
, 544 Mb/s multiplexed signal.
（ｂｌの二次信号は（８）の−次群の各音声信号の冗長
性を少（し、−次群信号２回線分を同し符号速度の１回
線に編制替えしたもので１音声信′シーの’＋Ｔ号化を
３〜４ピッ１−に低下して）ｉ：域圧縮をはかったもの
である。従ってフレーム同期パルスも低ヒツト化に相応
しい符号構成が選ばれ一般には（ａｌに示す一次群信号
のＦパルスとは別個の例えば図示のごときＧパルスが定
められる。中継装置４はこの二次信号が通るようにつく
られ、相手となる多重信号変換装置１゛に二次信号を伝
送するが中）１」［伝ｊｘ路は（ａｌの一次信号をその
ままでは通さないのが普通である。（Ｃ）は本発明によ
る二次信号の符号構成を示すものでそのフレーム同期パ
ルスは低ピノ１化信号の同期に必要なパルスＧに一次信
℃のフレーム同期パルスＦを付加した構成とし符号の形
式としては一次信号の符号形式をｌ！１足する形にｊｆ
ｆふ。(The secondary signal of bl is obtained by reducing the redundancy of each audio signal of the -order group in (8), and rearranging two lines of the -order group signal into one line with the same code speed.) The i: range compression is achieved by lowering the +T encoding of the 'C' to 3 to 4 pips 1-.Therefore, a code structure suitable for lowering the hit rate of the frame synchronization pulse is selected, and generally it is For example, a G pulse as shown in the figure is determined, which is separate from the F pulse of the primary group signal shown in FIG. Normally, the primary signal of (al) is not passed through the transmission path as it is. (C) shows the code structure of the secondary signal according to the present invention, and its frame synchronization pulse is The frame synchronization pulse F of the primary signal C is added to the pulse G necessary for synchronizing the low pinot 1 signal, and the code format is the code format of the primary signal plus l!1 jf
ffu.
また、多重変換装置１に一次側信号を二次側にバイパス
するスイッチＳａ、Ｓｂを設げておけば、たとえ多重変
換装置１の信号変換部に障害が起きてもスイッチＳａ、
Ｓｂを点線の方に切り替えれば伝送信号の符号形式に問
題が無いので少なくとも一次側信号の一回線が中継装置
４を通り生かされるので全回線が断になるという最悪の
状態は避けられる。Moreover, if the multiplex converter 1 is provided with switches Sa and Sb that bypass the primary side signal to the secondary side, even if a failure occurs in the signal converter of the multiplex converter 1, the switches Sa,
If Sb is switched to the dotted line, there will be no problem with the code format of the transmission signal, so at least one line of the primary signal will be kept alive through the relay device 4, and the worst situation where all lines will be disconnected can be avoided.
（ｆ）発明の効果
実施例で説明したごとく、本発明によれば多重信号変換
装置が障害でも最小限−次側一回線が容易に生かされる
のでその効果は大きい。(f) Effects of the Invention As explained in the embodiments, according to the present invention, even if the multiplex signal converter fails, at least one line on the next side can be easily utilized, so the effect is great.
第１図はデジタル多重信号変換伝送方式のプロ・ツク図
、第２図は信号のフレーム構成図である。
第１図において、１は多重信号変換装置、２は一次側回
線、３は二次側回線、４は中継装置、Ｓａ、ｓｂがバイ
パススイッチである。
第２図において、（ａ）は−次側信号、（ｂｌ、（Ｃ１
は二次側信号の構成例である。FIG. 1 is a block diagram of a digital multiplex signal conversion transmission system, and FIG. 2 is a signal frame configuration diagram. In FIG. 1, 1 is a multiplex signal converter, 2 is a primary line, 3 is a secondary line, 4 is a relay device, and Sa and sb are bypass switches. In FIG. 2, (a) is the negative side signal, (bl, (C1
is an example of the configuration of the secondary side signal.
Claims (1)
号変換装置において、二次側多重信号のフレーム同期パ
ルスの構成を一次側多重信号のフレーム同期パルスを含
む構成とし、装置の一次側多重入力回線の一つを二次側
出力回線に直結するスイッチを具備することを特徴とし
たバイパス式デジタル多重信号変換装置。In a digital multiplex signal converter in which the code transmission speed on the primary side and the secondary side are the same, the configuration of the frame synchronization pulse of the secondary side multiplex signal is configured to include the frame synchronization pulse of the primary side multiplex signal, and A bypass type digital multiplex signal conversion device characterized by comprising a switch that directly connects one of the input lines to a secondary side output line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14551483A JPS6037848A (en) | 1983-08-09 | 1983-08-09 | Bypass type digital multiplex signal converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14551483A JPS6037848A (en) | 1983-08-09 | 1983-08-09 | Bypass type digital multiplex signal converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037848A true JPS6037848A (en) | 1985-02-27 |
Family
ID=15386998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14551483A Pending JPS6037848A (en) | 1983-08-09 | 1983-08-09 | Bypass type digital multiplex signal converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037848A (en) |
-
1983
- 1983-08-09 JP JP14551483A patent/JPS6037848A/en active Pending
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