JPH0213999B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a branch connection system in which communications between a plurality of points transmitted by time division multiplex communication are mutually branched.

``Prior Art'' A conventional branching device used for multipoint communication on a digital private line has a single main station and fixed ports for a plurality of slave stations, and realizes a unidirectional branch line. With unidirectional branching, information from a terminal connected to the master station port could be simultaneously transmitted to terminals connected to multiple slave stations, but conversely, information from terminals connected to slave stations could be transmitted to the master station port. It was only possible to transmit information to a terminal connected to a terminal, but it was not possible to broadcast information to terminals connected to multiple slave stations. In other words, the conventional branching system was one-way branching from a master station to a plurality of slave stations.

FIG. 1 shows the principle of this unidirectional branching. Information from the master port M can be branched and transmitted simultaneously to a plurality of slave ports S ₁ and S ₂ by the selection circuit 11 . However, information from each slave port S ₁ and S ₂ can only be transmitted to the master port M. Which of the slave ports _S1 and _S2 to be selectively input to the master port M is determined by the S bit provided for each line and indicating the communication status.

In order to eliminate these drawbacks, the present invention realizes bidirectional branching in which any port can become a master station. The drawings will be explained in detail below.

"Principle of the Invention" FIG. 2 shows the principle of the invention, in which bidirectional branching is realized by a combination of unidirectional branches.
Figure 2A corresponds to an 8-wire branch of the conventional analog branch, and information from the master station port _M1 is branched by the selection circuit 11 to the slave station port _S1 and the selection circuit 12, and is input to the selection circuit 12. Main station port M ₁
The information from is output to the main station port _M2 . Also,
Information from main station port _M2 is selected by selection circuits 12 and 11.
This allows simultaneous transmission to slave port _S1 and master port _M1 . From slave port S ₁ to master port M ₁ by selection circuit 11, and from slave port S 1 to master port M 1.
Information can be transmitted from S ₂ to master port M ₂ by selection circuit 12 . In this case, slave port
If S ₁ and S ₂ are at the same location, this and main station port M ₁ ,
A bidirectional branch with _M2 will be made.

FIG. 2B shows the case where all the ports are used as master stations, and the master station ports M ₁ , M ₂ , and M ₃ are connected to selection circuits 11, 12, and 13, respectively, and selection circuit 1
1, 12, and 13 are interconnected. Any one master station port can simultaneously branch and transmit information to the remaining master stations. Such bidirectional branching with all ports as master stations will be referred to as a 4-wire branch.

This invention realizes the bidirectional branching shown in FIGS. 2A and 2B using time-division lines.

For example, as shown in Figure 3, interface 1 ₁
~1 _o , the time division multiplexed lines are input to the multiplexing circuit 14 and further time division multiplexed.
This time-division multiplexed signal is input to a branching device 15 to which the branching method according to the present invention is applied, and is branched into a plurality of predetermined time-division channels (time slots). The time division multiplexed signal from the branching device 15 is separated by a demultiplexing circuit 16, and each separated time division multiplexed signal is supplied to the interfaces ₂₁ to _2o . Interface 1 ₁ ~ 1 _o and 2 ₁ ~ 2 _o
and each form a pair. Multiplexing circuit 1
A plurality of predetermined, eg, dedicated channels (channels) in the time division multiplexed signal at the output of 4 may need to mutually diverge their information.

FIG. 4 shows an example of the branching device in FIG. The input time division multiplexed signal is supplied to the selector 17 and also to the first time slot switching circuit 18. The first time slot switching circuit 18 switches the time slots of a plurality of predetermined channels (for example, dedicated lines) for each frame in the input time division multiplexed signal into at least three predetermined consecutive time slots in the frame. Can be exchanged for lotto. For example, as shown in Fig. 5, one time slot consists of 8 bits in parallel from _b1 to _b8 , data from the master station M is placed in the i time slot, data from the slave station S1 is placed in the i+1 time slot, and data from the slave station _S1 is placed in the i+2 time slot. The data of slave station _S2 is replaced. In FIG. 3, each data of the master station M and the slave stations S ₁ and S ₂ exists distributed in one or more of the interfaces 1 ₁ to 1 _o .

The output of the first time slot switching circuit 18, the second
The output of the time slot switching circuit 19 is the selector 2.
1 and is supplied to the unidirectional branch implementation circuit 22. The unidirectional branch realization circuit 22 branches the data of one characteristic time slot i among the consecutive time slots i, i+1, and i+2 to the remaining consecutive time slots i+1 and i+2, and outputs the data, and At least a portion of each of the remaining consecutive time slots i+1 and i+2 is output as data of the specific time slot i. The unidirectional branch realizing circuit 22 is configured as shown in FIG. 6, for example. In FIG. 6, the parallel time-division signals from the time slots corresponding to the main station and the slave station are converted into serial time-division signals by the parallel-to-serial conversion circuit 23 as shown in FIG.
is input. When the circuit SbitCON26 in FIG. 6 detects that the line is in a communication state by the Sbit of each slave station S ₁ , S ₂ , S ₃ , it passes the information on that line as it is, and on the other hand, the Sbit allows the line to This circuit converts the information on the line to all 1s when it detects that there is no communication state. Through this control and the subsequent AND gate 27, the slave stations S ₁ , S ₂ ,
One from _S3 can selectively control information transmission on the main station side. On the other hand, data from each master station M is branched to three slave stations S ₁ , S ₂ , and S ₃ . The outputs of the circuits 24 and 25 are converted into parallel signals by a serial/parallel conversion circuit 28. This parallel signal means that data from either slave station S ₁ or S ₂ is sent to the i time slot for the main station, and data is sent to i time slot for the slave stations S ₁ , S ₂ , and S ₃ respectively.
The data of the master station M is supplied to each time slot of +1, i+2, and i+3, that is, the data of the master station M is branched and supplied to the slave stations S ₁ , S ₂ , and S ₃ .

The circuit 22 branched in one direction in this way (fourth
The output of FIG. 2 is input to the third time slot switching circuit 29. This circuit 29 performs the reverse of the time slot replacement performed by the first time slot replacement circuit 18. Therefore, the time slots of each master station and each slave station are returned to the time slot positions on the output time division multiplexed signal of the multiplexing circuit 14 and supplied to the multiplexing/demultiplexing circuit 16 via the selector 17.
Lines that do not require branching are output from the multiplexing circuit 14 to the multiplexing/demultiplexing circuit 16 via the selector 17. When the number of unidirectional branches exceeds the limit of the unidirectional branch realization circuit 22 (the number of branches is 3 in the example of FIG. 6), the output of the unidirectional branch realization circuit 22 is input to the second time slot switching circuit 19, and the The output is again input to the unidirectional branch realizing circuit 22. The following steps are repeated until the desired number of branches is obtained. The operating principle when the number of branches is 2, 4, or 7 is summarized in FIG. 9th
Figure A shows a case where the number of branches is two, and the branches of the unidirectional branch implementation circuit 22 are shown in FIG. In FIG. 9B, the number of branches is C, and the unidirectional branch realizing circuit 22 branches the data of the main station M to time slots i+1, i+2, i+3, as shown in FIG. 9b, The i+1 and i+2 are output to the slave stations S ₁ and S ₂ , and the time slot i+3 is input to the second time slot switching circuit 19, the time slot is replaced with i, and the time slot is again supplied to the unidirectional branch realization circuit 22.
Transfer that data to time slots i+1, i+
2, branches to i+3, and its time slot i+
1 and i+2 are supplied to slave stations S ₃ and S ₄ , respectively. FIG. 9C shows a case of 7 branches, and as shown in FIG. 9C, the input signal is input twice to the second time slot switching circuit 19, and the unidirectional branch realization circuit 22 performs branching three times.

Bidirectional branching according to the invention is implemented as follows. In FIG. 4, the signal from the multiplexing circuit 14 is converted by the first time slot switching circuit 18 to a time slot position suitable for the unidirectional branch realization circuit 22, and is input to the unidirectional branch realization circuit 22. Its output is sent to the second time slot switching circuit 19.
is also input, and its output and the output of the first time slot switching circuit 18 are selected by the selector 21 to realize bidirectional branching. For example, in the case shown in FIG. 10A (FIG. 2A), as shown in _FIG . Branched to slave station S ₁ , time slot i
The data of the main station _M1 branched to +2 is sent to the unidirectional branch realization circuit 2 via the time slot switching circuit 19.
2, and either this or the data of slave station _S1 is output from time slot i to master station _M2 .

In the case of FIG. 10B (FIG. 2B), in the first operation of the unidirectional branch realization circuit 22, the data of the main station _M1 of time slot i from the switching circuit 18 and the data from the switching circuit 19 two frames earlier data of time slot i+1 (data of main station _M2 ) and 1
The data of time slot i+1 of the previous frame (data of main station _M3 ) are transferred to time slot i, respectively.
Input from the selector 21 as i+1 and i+2. Data from main station _M1 is transferred to time slot i+1,
Branches to i+2 and becomes the main station at time slot i+1.
Data from _M2 or data from master station M3 at i+ ₁ is output to time slot i and sent to master station _M1 , and data from master station _M1 at time slots i+1 and i+2 is supplied to switching circuit 19. do.

The next operation of the unidirectional branch realizing circuit 22 is to transfer data from the switching circuit 18 to the main station M ₂ at time slot i, and from the switching circuit 19 to the data from the previous time slot i+1 (data from the main station M ₁ ). Input the data of time slot i+2 two frames ago (data of master station _M3 ) as data of time slots i, i+1, and i+2, respectively, and input the data of master station _M2 to time slots i+1 and i+.
The main station _M1 or _M3 data from time slot i+1 or i+2 is output from time slot i.

Furthermore, the next operation of the unidirectional branch realizing circuit 22 is as follows.
The data of the main station _M3 from the switching circuit 18 and the time slot i+ two frames before from the switching circuit 19
The data of master station _M1 of time slot i+2 and the data of master station _M2 of time slot i+2 one frame before are input as the data of time slots i, i+1, and i+2, respectively, and the data of master station _M3 of time slot _i1 are input. The data is branched to time slots i+1 and i+2 and inputted to the switching circuit 19.
+2 main station _M1 or _M2 is selected and output from time slot i.

Thereafter, the above-mentioned three-stage operation is repeated.

"Effects of the Invention" As explained above, according to the present invention, bidirectional branching can be realized by time division multiplexing of unidirectional branching circuits. Therefore, when it is necessary to transfer information from any terminal to each terminal in a broadcast manner, according to the present invention, bidirectional branching can be realized economically and efficiently.

[Brief explanation of drawings]

Figure 1 is a principle diagram showing a conventional unidirectional branch, Figure 2
3 is a block diagram showing a time division multiplex line, FIG. 4 is a block diagram showing an embodiment of the invention, and FIG. 5 is a diagram showing an example of the 8-bit parallel signal output from the first time slot switching circuit 18 in FIG. 4, and FIG. 7 is a diagram showing an example of a serial signal output from the parallel-to-serial conversion circuit 23 in FIG. 6, FIG. 8 is a diagram showing an example of an output parallel signal from the serial-to-parallel conversion circuit 28 in FIG. 6, and FIG. The figure shows an implementation example of unidirectional branching along with branching line settings, and FIG. 10 is a diagram showing an implementation example of bidirectional branching of the present invention together with branching line settings. M, M ₁ , M ₂ , M ₃ : Main station port, S, S ₁ ,
_S2 : Slave port, 18, 19, 29: Time slot switching circuit, 22: Unidirectional branch realization circuit.

[Claims]

1 A dome part 12 is provided in the center part, and the dome part 12
A voice coil attachment part 14 to which a voice coil is attached to the back surface is provided on the outer periphery of the voice coil attachment part 14, an edge part 15 is provided on the outer periphery of the voice coil attachment part 14, and an edge part 15 is provided on the outer periphery of the voice coil attachment part 14.
In the diaphragm 11 of the acoustic transducer, the edge fixing parts 16 are formed concentrically on the outer periphery of the edge part 15. The tangential planes b' and c' that intersect with the contact points b and c form a polyhedron having a protrusion on the front side of the diaphragm 11 in the portion where the edge portion 15 is evenly divided, and the center of the diaphragm 11 is formed with this polyhedron as one unit. A diaphragm for an acoustic transducer, characterized in that a polyhedral annular edge portion 15 is formed successively and rotationally symmetrically with respect to O.