JPS6037661B2 - Sample value conversion circuit - Google Patents

Sample value conversion circuit

Info

Publication number
JPS6037661B2
JPS6037661B2 JP56147840A JP14784081A JPS6037661B2 JP S6037661 B2 JPS6037661 B2 JP S6037661B2 JP 56147840 A JP56147840 A JP 56147840A JP 14784081 A JP14784081 A JP 14784081A JP S6037661 B2 JPS6037661 B2 JP S6037661B2
Authority
JP
Japan
Prior art keywords
sample value
conversion circuit
sampled
value conversion
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56147840A
Other languages
Japanese (ja)
Other versions
JPS5781788A (en
Inventor
敬彦 吹抜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Hitachi Ltd
Original Assignee
Hitachi Denshi KK
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK, Hitachi Ltd filed Critical Hitachi Denshi KK
Priority to JP56147840A priority Critical patent/JPS6037661B2/en
Publication of JPS5781788A publication Critical patent/JPS5781788A/en
Publication of JPS6037661B2 publication Critical patent/JPS6037661B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H15/00Transversal filters
    • H03H15/02Transversal filters using analogue shift registers

Landscapes

  • Color Television Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Description

【発明の詳細な説明】 本発明は標本値変換回路、更に詳しく言えば、ある位相
で標本化された標本値系列を、他の位相標本化された標
本値系列と同一の標本値系列変換する変換回路に係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample value conversion circuit, and more specifically, a sample value conversion circuit that converts a sample value series sampled at a certain phase into the same sample value series as a sample value series sampled at another phase. Related to conversion circuit.

例えばNTSC複合カラ・−テレビジョン信号を−定の
標本化周波数(例えば色副搬送波周波数ナScの4倍)
で標本化する場合、その位相には自由度があるが、通常
は1,Q軸、あるし、は(R−Y),(B−Y)軸で行
なう場合が多い。色信号の帯城を厳密に規格に合わせる
場合には前者が望ましく、回路の簡単化のためには後者
が望ましい。さて、上述の如く少くとも2つの異なる位
相の組で標本化方式があるので、これらを相互変換する
必要性が生まれる場合がある。従来この方法として、色
信号を復調し、Y,1,Qの各成分、あるいはY,(R
−Y),(B−Y)の各成分を得て、この1,Q、およ
び(R−Y),(B−Y)をNTSCの規格に従った係
数を乗じてマトリクス演算を行ない変換する方法がとら
れていた。
For example, an NTSC composite color television signal has a constant sampling frequency (e.g., four times the color subcarrier frequency NaSc).
When sampling with , there is a degree of freedom regarding the phase, but it is usually performed on the 1 and Q axes, or on the (R-Y) and (B-Y) axes. The former is preferable when the band width of the color signal strictly conforms to the standard, and the latter is preferable for simplifying the circuit. Now, as mentioned above, since there are sampling methods using at least two different phase sets, it may be necessary to mutually convert these. Conventionally, this method demodulates the color signal and converts each component of Y, 1, and Q, or Y, (R
-Y) and (B-Y) are obtained, and these 1, Q, and (R-Y), (B-Y) are multiplied by coefficients according to the NTSC standard and converted by performing matrix operation. A method was taken.

しかし、この場合、再び色副搬送波を変調して他の軸に
おける標本化を得る必要があった。
・本発明はある位相で標本化された標本値系列を一
旦復調することなく、直接地の位相で標本化された標本
値系列を得るための変換回路を実現することを目的とす
る。
However, in this case it was necessary to modulate the color subcarrier again to obtain sampling in the other axis.
- An object of the present invention is to realize a conversion circuit that directly obtains a sample value series sampled at a ground phase without demodulating the sample value series sampled at a certain phase.

すなわち、たとえばカラーテレビジョン信号の1,Q軸
で標本化された値系列…g‐,,軟,&,鞍,・・・・
・・から、直接(R−Y),(B−Y)軸での標本値系
列・・・h‐.,へ,h,,h2,……を得ることを目
的とする場合である。
That is, for example, a value sequence sampled on the 1,Q axis of a color television signal...g-,, soft, &, saddle,...
..., directly sample value series on the (R-Y) and (B-Y) axes...h-. , to,h,,h2,...

本発明は上記目的を達成するため、ある位相で標本化さ
れた複数個の標本値信号(標本値系列と呼ぶ)を遅延素
子に加え遅延された標本系列に一定の係数を乗じ、すな
わち定められた値で加重して加算することによって、異
なる位相で標本化された標本系列信号に実質的に等しい
標本系列信号に変換する如く構成したものである。
In order to achieve the above object, the present invention adds a plurality of sample value signals sampled at a certain phase (referred to as a sample value sequence) to a delay element, and multiplies the delayed sample sequence by a certain coefficient. By weighting and adding the sample sequence signals with the different phases, the sample sequence signals are converted into sample sequence signals that are substantially equal to the sample sequence signals sampled at different phases.

本発明によれば変換回路が単に遅延素子と簡単な系数付
加回路のみによって容易に構成される。以下、本発明を
図面を用いて詳細に説明する。
According to the present invention, a conversion circuit can be easily constructed using only a delay element and a simple series addition circuit. Hereinafter, the present invention will be explained in detail using the drawings.

第1図はNTSC複号カラーテレビジョン信号ナ上を色
副搬送波周波数ナscの4倍の標本化周波数で標本化す
る場合の標本系列の様子を示すもので、実線で示す系列
歌,9,…・・・鞍,・・・・・・は1,Q軸で標本化
を行う場合、点線で示す系勿血。,h,,・・・…も,
・・・・・・は(R−Y),(B−Y)軸で標本化を行
う場合を示す。これらの系列の関には一定の関係が存在
し、下述の原理により、一方の標本系列から他の標本系
列に変換できる。標本化定理に従えば、源波形〆tはs
tを標本化関数(=sint/f)としてナF・Z g
iS(t−iT) ………{111三」 ぬで表
わされる。
Figure 1 shows the sample sequence when an NTSC decoded color television signal is sampled at a sampling frequency that is four times the color subcarrier frequency. ...Saddle, ...... is 1, and when sampling is performed on the Q axis, the system is indicated by the dotted line. ,h,,...also,
. . . indicates a case where sampling is performed on the (RY) and (BY) axes. A certain relationship exists between these series, and one sample series can be converted to another according to the principle described below. According to the sampling theorem, the source waveform 〆t is s
With t as the sampling function (=sint/f), F・Z g
iS(t-iT) ......{1113'' Represented by nu.

Tは標本化間換で、この場合汀/2で正規化して示して
いる。従って、信号系列・・・h‐,,ho,h,,h
2……は、Q‐1’Qo’Q・・・…・を第2図の如く
定義してhk=.Z g肌 Q;・ ……■・
ニくめで表わされる。
T is the sampling interval, which in this case is normalized by T/2. Therefore, the signal sequence...h-,,ho,h,,h
2... defines Q-1'Qo'Q... as shown in Figure 2, and hk=. Z g skin Q;・ ……■・
It is expressed in diagonals.

Q, はiの絶対値が大きくなるのに従い小さくなるか
らN .・・・・・【31h
k三.Z gk+i Q‐11==一N となる。
Since Q, becomes smaller as the absolute value of i becomes larger, N.・・・・・・【31h
k3. Z gk+i Q-11==1N.

したがって、標本系列gkからの標本系列hkが演算に
よって容易に実現できることが分る。
Therefore, it can be seen that the sample sequence hk from the sample sequence gk can be easily realized by calculation.

第3図は本発明による標本値変換回路の一実施例の回路
構成を示す図である。いま、入力端子1よりアナログ標
本値系列g‐,,動,封,&……が加えられる。
FIG. 3 is a diagram showing the circuit configuration of an embodiment of the sample value conversion circuit according to the present invention. Now, the analog sample value series g-, , dynamic, seal, &... is added from the input terminal 1.

これはアナログシフトレジスタ3で遅延される。アナロ
グシフトレジスタ2は標本化周期の遅延時間を有する遅
延素子を複数段縦競的に接続したものと考えて良い。各
段の出力は荷重抵抗3で係数を掛けて加算され、他の標
本値系列h‐,,L,h,,h2・・・・・・として出
力端子4に出力される。本発明は上記実施例に限定され
るものでなく種種の態様で実施できる。
This is delayed by analog shift register 3. The analog shift register 2 can be thought of as a plurality of delay elements connected in tandem in multiple stages, each having a delay time equal to the sampling period. The outputs of each stage are multiplied by a coefficient by a load resistor 3, added, and outputted to an output terminal 4 as other sample value series h-, , L, h, , h2, . . . . The present invention is not limited to the above embodiments, but can be implemented in various ways.

例えば次のような実施態様で実現できる。{1} アナ
ログ的な変換に代り、A/D変換された信号系列に対し
てディジタル的な変換を行なうことも可能である。
For example, it can be realized by the following embodiment. {1} Instead of analog conversion, it is also possible to perform digital conversion on the A/D converted signal sequence.

この場合、乗算回路が問題となるが、読出専用メモリを
素くという通常の方法のほかシフトと加減算によって係
数を得る方法も広く知られている。たとえば、第2図よ
りQo =0.94562であるが、これはQo i0
.94562ニ1−1/16(十1/64)と近似でき
、同様にQ,,Q2もo,=一0.25370=一1/
4 o2 =0.14650=1/8(十1/64)のよう
に近似でき、それぞれデータを所定のビット数だけずら
して加算すればよい。
In this case, the multiplication circuit becomes a problem, but in addition to the usual method of dispensing with a read-only memory, methods of obtaining coefficients by shifting, addition, and subtraction are also widely known. For example, from Fig. 2, Qo = 0.94562, which is Qo i0
.. 94562 Ni1-1/16 (11/64), and similarly Q,,Q2 can be approximated as o,=-0.25370=-1/
It can be approximated as 4 o2 = 0.14650 = 1/8 (11/64), and each data may be shifted by a predetermined number of bits and added.

■ 式‘1},【2’,{3}‘ま特にテレビ信号に限
らず一般に成立するから本方式はテレビ信号に限らず、
任意の信号について成立することは原理的にも明らかで
ある。
■ Equations '1}, [2', {3}' hold true in general, not just for TV signals, so this method is applicable not only to TV signals, but also to TV signals.
It is clear in principle that this holds true for any signal.

(3} 第3図に示した実施例における構成はトランス
バーサルフィルタ形式であるが、これと等価な特性を示
す非巡回型フィル夕は他にもいろいろあり公知の方法で
構成できる。
(3) Although the configuration in the embodiment shown in FIG. 3 is of a transversal filter type, there are various other non-recursive filters that exhibit characteristics equivalent to this type, and can be configured using known methods.

以上述べた如く、本発明は簡単な回路で標本化の位相の
異なる信号系列間の変換を行ないうる点、実用に供して
極めて有効である。
As described above, the present invention is extremely effective in practical use because it allows conversion between signal sequences having different sampling phases with a simple circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の原理説明のための波形図、第
3図は本発明の一実施例の回路図である。 1・・・入力端子、2・・・遅延回路素子、3・・・荷
重抵抗、4・・・出力端子。 素ー図 芥2図 第3図
1 and 2 are waveform diagrams for explaining the principle of the present invention, and FIG. 3 is a circuit diagram of an embodiment of the present invention. 1... Input terminal, 2... Delay circuit element, 3... Load resistance, 4... Output terminal. Drawing 2, Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1 ある位相で標本化された第1の標本化信号系列を、
上記ある位相に対して一定の位相差を有して標本化され
た第2の標本化信号系列に変換する変換回路において、
上記第1の標本化信号系列を複数の遅延素子に導き、
上記複数の遅延素子の出力を上記位相差に対応する標本
化関数の値で加重し、総和をとることにより、上記第2
の標本化信号系列を得ることを特徴とする標本値変換回
路。
1 The first sampled signal sequence sampled at a certain phase is
In the conversion circuit that converts into a second sampled signal sequence sampled with a certain phase difference with respect to the above-mentioned certain phase,
guiding the first sampled signal sequence to a plurality of delay elements;
The second
A sample value conversion circuit characterized in that it obtains a sampled signal sequence.
JP56147840A 1981-09-21 1981-09-21 Sample value conversion circuit Expired JPS6037661B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56147840A JPS6037661B2 (en) 1981-09-21 1981-09-21 Sample value conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56147840A JPS6037661B2 (en) 1981-09-21 1981-09-21 Sample value conversion circuit

Publications (2)

Publication Number Publication Date
JPS5781788A JPS5781788A (en) 1982-05-21
JPS6037661B2 true JPS6037661B2 (en) 1985-08-27

Family

ID=15439433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56147840A Expired JPS6037661B2 (en) 1981-09-21 1981-09-21 Sample value conversion circuit

Country Status (1)

Country Link
JP (1) JPS6037661B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4880578U (en) * 1971-12-29 1973-10-02
JPS4977965U (en) * 1972-10-24 1974-07-05

Also Published As

Publication number Publication date
JPS5781788A (en) 1982-05-21

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