JPS6035597A - Multilayer wiring structure - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a multilayer wiring structure, and particularly to a structure for connecting upper and lower wiring layers through fine through holes.

[Background technology]

Semiconductor integrated circuit devices require a multilayer wiring structure in which an upper wiring layer and a lower wiring layer are formed above and below an insulating film, but at the same time, these upper and lower wiring layers must be electrically connected to each other through the insulating layer. There is. For this reason, in conventional multilayer wiring structures, through holes are formed in the insulating film on the lower wiring layer, and the upper wiring layer is formed on the through holes to directly connect the upper and lower wiring layers ( (Japanese Unexamined Patent Publication No. R1353-81094).

However, with the increasing integration of single-circuit elements, miniaturization of the through-hole diameter was required, and as a result, the dry etching method began to be used for processing the through-holes, as shown in Figure 1. Thus, the shape of the through hole 3 opened in the insulating film 2 becomes steep. For this reason, if the upper wiring layer 5 is formed on the lower wiring layer 4 by a vapor deposition method or the like, so-called step breaks may occur due to poor coverage, and it is conceivable that the upper wiring layer 5 may be disconnected at the through-hole portion. In the figure, 1 is a substrate such as a ceramic wafer or a silicon wafer.

[Purpose of the invention]

The purpose of the present invention is to prevent disconnection due to breakage of the upper wiring layer within the through hole even when the through hole becomes finer and more steep in shape, and to provide a multilayer wiring structure that is more reliable than this trap. There is a particular thing.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[vA essentials of invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by filling the through holes formed in the insulating film between the upper and lower wiring layers with internal pressure solder and making contact between the upper and lower wiring layers through this solder, the through holes can be made finer and steeper. However, it prevents breakage or disconnection of the upper wiring layer.

This improves the reliability of the multilayer wiring structure.

〔Example〕

Figures 2 to 0 show embodiments of the present invention in the order of the manufacturing process.
First, a first wiring layer (lower wiring layer) 13 is formed in a predetermined pattern shape on a substrate 1 using a photoresist film 12 as a mask, as shown in the hole in the figure. . This first wiring layer 13 is a Ti film 14
, (' II film 15 r Au film 16 is sequentially stacked by vapor deposition method, etc., and then the photoresist film 12 is removed together with the T1 film 14, Cu film 15, and Au film 16 thereon by a so-called lift-off method, as shown in FIG. ). The first wiring layer 13 may be formed by a mask evaporation method. Ti film 14 is a substrate (ceramic)
The CLI film 15 ensures wettability with solder, which will be described later, and the Au film 16 prevents the Cu film 15 from oxidizing. Sin or PS
An insulating film 17 such as G is formed on the entire surface, and then the same figure (C) is formed.
A through hole 18 is formed in the insulating film 17 on the first wiring layer 13 which requires a contact as shown in FIG.

Next, as shown in FIG. 00, the insulating film 17 that matches the through hole 18
A solder (Pb/Sn) film 19 is partially formed thereon. This solder film 19 is formed by a mask vapor deposition method, but may also be formed by a lift-off method using photoresist. When this is then heated to melt the solder film 19, the solder is repelled by the solid insulating film 17 and collected on the upper surface of the first wiring layer 13, which has good wettability. The solder 19 is filled into the through hole 18 as shown in Q. At this time, by appropriately determining the area and thickness of the solder film 190, the half Hj amount becomes approximately equal to the volume of the through hole 18.
Therefore, the upper surface of the solder 19 substantially coincides with the upper surface of the insulating film 17 and becomes flat. Also.

An alloy layer 20 of Ti and Cu is formed by heating.

Next, as shown in FIG. [F], the second wiring layer (upper wiring 15)
21 is formed on the insulating film 17 by a 7-off method. The second wiring layer 2 is made up of a CLI film 22 and a T1 film 23, and is also formed on the through hole 18. When it is heated, the solder 19 is melted and the second wiring layer 22 is formed.
connected to. At this time, C from the Cu film 22 in the solder 19
u is sucked in, the solder 19 becomes larger, and the connection becomes tighter.

As a result.

As shown in FIG. The planar structure is shown in FIG. 3, and the line 1111 in the same figure is the cross-sectional line in FIG.

Therefore, according to this two-layer wiring structure, through hole 1
Even if the through hole 18 is made finer and steeper by dry etching, the upper surface of the through hole 18 is flattened by filling the solder 19 into the through hole 18.

When the second wiring layer 21 is formed, there will be no breakage in K (breakage will also be prevented), thereby making it possible to construct a highly reliable multilayer wiring structure.

〔effect〕

(1) The through-holes formed in the insulating film between the upper and lower wiring layers are filled with internal pressure solder to flatten the upper surface of the through-holes. It is possible to prevent this problem and obtain a highly reliable multilayer wiring structure.

(2) A solder film is formed on the insulating film including the through-holes, and then melted, and the solder is filled into the through-holes using the solder's individual properties, making the above structure easy. can be formed into

t31 Since disconnection of the wiring layer can be prevented regardless of the miniaturization and steepness of the through holes, miniaturization of semiconductor integrated circuit devices, that is, high integration can be realized.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and it is possible to make various changes without getting across the gist of the invention. Needless to say, for example, solder is Pb
/Sn solder and other solders can also be used. Also, above,
The lower 6-metal arrangement may be made of A2 material, or may be made of other metals as long as they are easily compatible with solder and do not cause solder migration. Ceramic heavy board 1
1. In order to flatten the surface, glass or the like may be applied before forming the first wiring layer.Furthermore, instead of solder, a material that exhibits fluidity at a relatively low heating temperature and is easy to cut with the underlying metal. It is also possible to use metal materials that can be embedded into the through-holes.

For example, easily fusible metals, hard solders, etc. may be used after considering the melting point of the underlying metal layer. Although the description has been given of the case where the present invention is applied to a semiconductor device, the present invention is not limited thereto, and can also be applied to a multilayer wiring structure of a general electronic circuit board.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining defects in the conventional structure. <rx) FIG. 2 (4) - Cross-sectional views for explaining the structure of the present invention in the order of manufacturing steps. FIG. 3 is a plan view. 11... Ceramic cutting board, 12... Photoresist film. 13... First wiring layer (lower wiring layer), 17... Insulating film. 18...Through hole, 19...Solder, 21...
Second wiring layer (upper wiring layer). 1 [4 zo / Figure 3 /, 9

Claims (1)

[Claims] 1. An upper wiring layer and a lower wiring layer are formed above and below an insulating film, respectively, and the upper and lower wiring layers are connected and electrically connected via through holes formed in the insulating film. In the multilayer wiring structure, the through hole is filled with solder, and the solder is applied to the upper layer through the solder. A multilayer wiring structure characterized by connecting each wiring layer below. 2. The multilayer C-line structure according to claim 1, in which the upper surface of the solder is substantially aligned with the upper surface of the insulating film. 3. The solder is selectively formed in a film on the through hole and the part on the insulating film containing the solder, and then heated and melted to fill the through hole.
Multilayer wiring structure as described in section.