JPS6034650U - input/output device - Google Patents
input/output deviceInfo
- Publication number
- JPS6034650U JPS6034650U JP12571083U JP12571083U JPS6034650U JP S6034650 U JPS6034650 U JP S6034650U JP 12571083 U JP12571083 U JP 12571083U JP 12571083 U JP12571083 U JP 12571083U JP S6034650 U JPS6034650 U JP S6034650U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output device
- output
- connector
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の装置を示すブロック図、第２図はこの考
案の一実施例を示すブロック図である。
１・・・ＣＰＵ、２・・・共通バス信号線、３−１．３
−２・・・それぞれＩｌｏ、４−１．４−２・・・それ
ぞれアドレス設定スイッチ、５−１．５−２・・・それ
ぞれコネクタ。尚、各図中同一符号は同−又は相当部分
を示す。FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a block diagram showing an embodiment of this invention. 1...CPU, 2...Common bus signal line, 3-1.3
-2...Ilo, respectively, 4-1.4-2...Address setting switches, respectively, 5-1.5-2...Connectors, respectively. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
出力装置が接続され、上記中央処理装置と外部の装置と
の間に上記複数の入出力装置のいずれかの入力装置を介
してデータの入出力を行う場合に用いられる入出力装置
において、当該入出力装置と外部の装置とを接続するケ
ーブルを当該入出力装置に着脱自在に接続するコネクタ
と、 このコネクタ内に設けられ、上記当該入出力装置からの
複数の導線の各導線を所定の電位の電源に対し閉接又は
開放することによって、当該入出力装置のアドレスに対
応するビットパターンのビット並列の信号を設定するア
ドレス設定スイッチとを備えたことを特徴とする入出力
装置。[Claims for Utility Model Registration] A plurality of input/output devices are connected to a single central processing unit via a common bus, and a plurality of input/output devices are connected between the central processing unit and an external device. In an input/output device used when inputting/outputting data via any input device, a connector for detachably connecting a cable connecting the input/output device and an external device to the input/output device; Bit parallelization of the bit pattern corresponding to the address of the input/output device by connecting or opening each of the plurality of conductors provided in this connector from the input/output device to a power source of a predetermined potential. An input/output device comprising an address setting switch for setting a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12571083U JPS6034650U (en) | 1983-08-11 | 1983-08-11 | input/output device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12571083U JPS6034650U (en) | 1983-08-11 | 1983-08-11 | input/output device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6034650U true JPS6034650U (en) | 1985-03-09 |
Family
ID=30286105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12571083U Pending JPS6034650U (en) | 1983-08-11 | 1983-08-11 | input/output device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6034650U (en) |
-
1983
- 1983-08-11 JP JP12571083U patent/JPS6034650U/en active Pending
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