JPS6033720A - Automatic level control circuit - Google Patents

Abstract

PURPOSE:To attain a highly stable circuit by using a control signal generating circuit comprising plural signal level detecting circuits. CONSTITUTION:The signal level detecting circuit 6 inputs an output signal VO of an amplifier circuit 3 to a base of a detection transistor (TR)Q4 via a coupling circuit comprising a capacitor C6 and a diode D2 and an input resistor R5 across which a TRQ5 is connected in parallel, and a collector of the TRQ4 grounded via a capacitor C5 outputs a control signal Vc. Further, the signal level detecting circuit 7 inputs the output signal VO of the amplifier 3 to the base of a detection TRQ6 grounded via a resistor V6 through a coupling circuit comprising a capacitor C7 and a diode D3 and also an input resistor R7, and an output Vc2 is outputted to a base of the TRQ5 of the signal level detection circuit 6 from the collector of the TRQ6.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to automatic level control circuits.

[Prior art]

Originally, an automatic level control circuit (hereinafter referred to as an ALC circuit) operates to keep the level of output No. 1 constant even when the level of an input signal fluctuates.

The operation of this ALC circuit is determined by the characteristics of the signal level detection circuit.

FIG. 1 is a circuit diagram showing an example of a conventional ALC circuit.

The input signal v1 inputted to the input terminal 1 is inputted to the attenuation circuit 2 via the coupling capacitor C1, amplified by the amplifier circuit 3, and outputted from the output terminal 5 as an output signal V1 via the coupling capacitor C2. During this period, the output 1 of the amplifier 3 is input to the signal level detection circuit 4, detected by the transistor Q1, and generates the control signal vc, which drives the transistor Q2 of the attenuation circuit 2 and controls the transistor Q2. By changing the resistance between the vector and emitter (CE), the seven levels of the input signal to the amplifier circuit 3 can be controlled. In other words, when the output signal v0 is negative and transistor Q1 operates, transistor Q2 operates and the resistance between CE and C of transistor Q2 becomes smaller.
Level control is automatically performed from input reconnaissance low to output low.

FIG. 2 shows the relationship between the input signal v0 of the signal level detection circuit 4 (same as the output No. 100 V of the amplifier circuit 3) and the output control signal V. The amplifier circuit output V is the level at which the transistor Q1 operates (this is called the threshold level of the No. 100 level detection circuit) vo. Until it reaches
The signal level detection circuit 4 does not output, and when the value exceeds ■, the signal level detection circuit 4 operates, and since the output signal vc becomes large, the attenuation circuit 2 is operated, and the input level of the amplifier circuit 3 is controlled. Output signal V. - control.

FIG. 3 shows the relationship between the input signal vI and the output signal V. As the input signal vi increases, the output signal V by the amplifier circuit 3 increases linearly, but when the output signal V exceeds the threshold level v, the signal level detection circuit 4 detects the attenuation circuit 2. To operate, the output signal v
The level of 0 can be suppressed. Further, the change Δvo when the input signal v is changed is called the ALC effect, and the smaller Δvo is, the better.

FIG. 4 is a time chart showing changes in the output signal v0 and l1jlj control signal vccD. When the output 100 v0 increases instantaneously at t=o, the control signal vc increases with a certain time reduction determined by the presence and resistance included in the circuit. It shows that it is stable.

Figure 5 shows input signal V and output signal V. 2 is a time chart showing the liquefaction of When the input multiplier Vt suddenly increases when t=o, the output signal v0 suddenly increases, but the control signal vc increases, and in order to drive the attenuation circuit 2 and attenuate the input, the circuit must It becomes stable at t=C2 depending on the time constant. (The time required for the output 1 to reach stability in response to a change in the input signal is called the response time.) In Fig. 5, C2
time of? If you try to make it as short as 02', the circuit operation will be vibrational υ as shown by the dashed line in the figure.
In extreme cases, the output signal V may drop to zero, as shown by the two-dot chain line V' in the figure. In this case, the time CI until the output signal V stabilizes is C2
The time required is several tens to hundreds of times longer than C2'.

As explained above, the operation of this ALCN path is governed by the characteristics of the 1C level detection circuit 4. However, in the conventional ALC circuit, as described above, the signal level detection circuit 4 is the only one, and does not fully satisfy the characteristics of the ALC circuit.

By the way, the output signal V with respect to the level fluctuation of the input signal V. In order to reduce the level fluctuation Δv0 (see FIG. 3), the gain of the closed circuit forming the ALC circuit must be increased. On the other hand, if the gain of the circuit is increased, the circuit approaches an unstable point where oscillation occurs, and the stability of the circuit is impaired.

In conventional ALC circuits, the gain of the closed circuit is often set close to the unstable point in order to reduce Δvt. Therefore, as shown in FIGS. 4 and 5, when a large input signal is instantaneously applied, the circuit becomes unstable, such as oscillation. This is input No. 100 V
The same is true when attempting to shorten the response time to fluctuations in the level of , and if the attempt is made to shorten it, the output signal will oscillate or oscillate and become unstable.

In other words, in the conventional ALCl circuit, if an attempt is made to reduce the level fluctuation of the output No. 1 in response to the input signal, or to shorten the response time to the level fluctuation of the input No. 100, the circuit becomes unstable, and the result is sufficiently satisfactory. There is a problem in that it is not possible to obtain an ALCl path with l characteristics.

[Purpose of the invention]

The purpose of the present invention is to solve the problems of the prior art.

This problem is solved by using a control 1 signal generation circuit consisting of a plurality of signal level detection circuits, and the level fluctuation of the output signal with respect to the input signal is small, and the response time of the output signal with respect to the level fluctuation of the input signal is shortened. The object of the present invention is to provide a stable ALC circuit.

[Structure of the invention]

The ALC circuit of the present invention includes an attenuation circuit in which the amount of signal attenuation is controlled by a control signal, an amplification circuit that amplifies the output signal of the attenuation circuit, and a large @ of the output No. 4 of the amplification circuit. The control signal generation circuit includes a plurality of No. 100 level detection circuits that output the control signal, and a control signal generation circuit that outputs the control signal.

[Explanation of Examples]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a circuit diagram of the first embodiment of the present invention. Components that are the same as those in the conventional example shown in FIG. 1 are given the same reference numerals.

The embodiment of this pile 1 includes an attenuation circuit 2 whose signal attenuation is controlled by a control ill signal V, an amplification circuit 3 that amplifies the output signal of this attenuation circuit 2, and an output signal of this amplification circuit 3. Two signal level detection circuits 6 and 7 that detect the magnitude of V
Output the empty allocation signal V τ? till I'fl
It is composed of the IN signal generating circuit 8 and the entire circuit.

The Ig level detection circuit 6 receives the output signal V of the amplifier circuit 3. is connected to a detection transistor Q through a coupling circuit consisting of a capacitor C6 and a diode D2, and a human resistance ratio 5 in which a transistor Q5 is connected in parallel between both ends of the coupling circuit.
A control signal v is input from the core lefter of the transistor Q4, which is input to the base of the transistor Q4 and is grounded via the capacitor C5.
ct output.

In addition, the A100 level detection circuit 7 detects the output 1HM of the amplifier 3.
V k is input to the base of a detection transistor Q6 which is grounded via a resistor R6 through a coupling circuit consisting of a capacitor C7 and a diode D3 and an input resistance ratio of 7,
Output vC2k, 'I' from the collector of transistor Qa
The signal is output to the base of the transistor Q5 of the f1 level detection circuit 6.

That is, this embodiment differs from the conventional circuit shown in FIG. The point is that the transformer driven by V2 and the transistor Qst are connected in parallel.

FIG. 7 is a diagram showing the relationship between the human input signal V of the control signal generation circuit 8 and the control No. 100 vc, and also shows the characteristics of the outputs vc2 and vcm of the signal level detection circuits 6 and 7 alone. As is clear from the figure, the signal level detection circuit 7 sets its threshold level voi to the threshold level V of the signal level detection circuit 6. 2, and the change in vc with respect to the change in input V is larger than the change in vc2.

Therefore, the output of the amplifier circuit 3 is 1V. (i.e., the input v0 of the signal level detection circuit), when the threshold level v02 is reached, the transistor Q
4 operates, and thereafter the control signal vc is operated along the straight line vc2 in FIG. 7 until reaching the threshold level v0□.
is output. And input V. is the threshold level V.

When □ is reached, transistor Q6 operates and draws the base current of transistor Q5, so transistor Q5 is turned on. Input resistance Rr of transistor Q4
, and the resistance value of the input resistance ratio 5 effectively becomes small, so that the control signal vc4-1 suddenly increases as shown in FIG.

As a result, according to the 21st embodiment, the signal voltage V.

Even if there is a sudden change in the signal level, the signal level detection circuit, that is, the control signal generation circuit operates accordingly, so that an ALC circuit with small level fluctuation Δvo can be obtained.

The characteristics obtained in this example will be explained below.

Figure 8 shows the human input signal vi of the ALC circuit and the output signal V.

shows the relationship between Output signal V. is the threshold level V 02
When the voltage exceeds the level, the level detection circuit 6 outputs an output v0□, so that the output signal v0 is kept constant. Furthermore, when the input signal V is large and the output signal V exceeds the threshold level v0□, the level detection circuit 7 outputs vcl
lr, output, so the control from the level detection circuit 6 (ll
When VC is large, the output signal V even with strong input.
is kept constant, the value of the level fluctuation ΔV becomes very small.

Figure 9 shows output No. 1J V. and the output V of the control signal generation circuit
A time chart showing all the changes. The temporal change in the output V of the control ↑ signal generation circuit is slow when the input is weak (from t=o to t=Ca in the figure), and fast when the input is strong.

(Between t=c4 and t=CS in the figure.) This means that
Operation of transistor Q4 when transistor Q4 alone operates in response to changes in weak input, and when base input resistor 5 is short-circuited by the output of transistor Q6, which operates in response to changes in strong input. This is due to the difference in

Figure 1O shows the input signal v1◆ and the output 1M V. 2 is a time chart showing changes in . When the input signal vI suddenly increases at t=o, the signal level detection circuit 6 operates until t=C6, and the attenuation circuit 2 operates according to its output vc2, and the output signal V gradually decreases. maintained at a certain level. Next, when Vmu changes rapidly at t=C7, the level detection circuit 7 operates from t=c7 to t=C8, and outputs a signal ■. The control signal V from the level detection circuit 6 is controlled by □, and the time constant changes, and due to the control signal vc, the reduction circuit 2 operates, and the output 1 level v0 sharply decreases. And the output signal V.

is the threshold voltage v of the 1st level detection circuit 7 when t=CS
When the voltage falls below 0□, only the signal level detection circuit 6 operates, and the output signal V becomes stable at t- et al. At this time, the time required for stabilization is determined by the signal level detection circuit 6
Compared to when only the signal level detecting circuit 7 operates from t=c7, the 1H level detecting circuit 7 operates until t=c8 and the time constant of the signal level detecting circuit 6 is short-circuited, so the time constant is shorter.

FIG. 811 is a circuit diagram of a second embodiment of the present invention. Note that the same components as in the conventional example shown in FIG. 1 are given the same reference numerals.

This embodiment includes a control signal generation circuit 11 consisting of two No. 100 level detection circuits 9 and 10.

The signal level detection circuit 9 includes a transistor Q71.
Diode D4. Resistor” 8 + capacitor C8C9
The signal level detection circuit wr10 consists of a transistor Q a + a diode D6 . Resistance 9. kL1
o* Consists of capacitor 0101011.

The main points in which this embodiment differs from the first embodiment shown in FIG. 6 are as follows:
Level 1 detection time W! output of rlO (resistance) 1194
The reason is that the signal is outputted to the base of the transistor Q70 of the signal level detection circuit 9 via the signal level detection circuit 9.

Therefore, according to this embodiment, as shown in FIG.
If the g level detection circuit MIO is not set and only the signal level detection circuit 9 is used, the threshold level V
. By adding the signal level detection circuit 1O, the control number 1N vc is output according to the straight line 3 with 3 tM, and the input signal V. When becomes large, transistor QB operates and draws the base current of transistor Q7, so the level at which transistor Q7 operates, that is,
For example, the threshold level is V. A big shi like 4,
The control signal V 1 is output according to the straight line ◯ in FIG. 12.

That is, according to this embodiment, the threshold level of the signal level detection circuit can be controlled by the output of another added signal level detection circuit, forming the desired control system and obtaining a stable ALC circuit. It will be of great help above.

FIG. 13 is a circuit diagram of a third embodiment of the present invention. Note that the same components as in the conventional example shown in FIG. 1 are given the same reference numerals.

This embodiment includes a control signal generation circuit 14 consisting of two signal level detection circuits 12 and 13.

The signal level detection circuit 12 includes a transistor Qe.
, diode D6. Resistor 11 R12 Capacitor C1
The 1g level detection circuit 13 consists of 2C13, transistor Q1o + Qi1+ diode D7
．． It consists of resistors R13, R'14° and capacitors C14, C1B, and the collector and emitter of the transistor Qlo are connected to the connection point between the collector of the transistor Q9 and the resistor R11, and to the other ends of the resistors LL and l, respectively. .

The main points in which this embodiment differs from the first embodiment shown in FIG. 6 are as follows:
A resistor 1t111r is connected to the collector of the detection transistor Q9.
, and a transistor QIG is connected in parallel between both ends thereof, and the base of the transistor QIO is driven through a circuit consisting of an output sound resistance R13 of a detection transistor Qu and a capacitor CI4.

Therefore, according to this embodiment, as shown in FIG. 14, when the signal level detection circuit 13 is not added and only the signal level detection circuit 12 is used, when the output V of the amplifier circuit 3 suddenly increases. , transistor Q9 operates,
As shown by the straight line ■, there is a certain time constant (determined by the product of the resistor R11 and the capacitor C12) that slowly reaches a steady state after t, since the No. 1 level detection circuit 13 is added. , transistor Qt by the output of transistor Qll.

turns on, short-circuits the resistor R11, and effectively reduces its resistance value, so the time constant becomes small and the control signal v0 quickly becomes a steady state as indicated by the straight line ■.

That is, according to this embodiment, the output V of the signal level detection circuit. Since the response time to the level change of the input V, can be forcibly controlled by the output of the other added signal level detection circuit, it is possible to can be obtained easily.

In the above embodiment, the case where two signal level detection circuits are combined as the control signal generation circuit has been described, but as is clear from the above description,
In accordance with the required characteristics, the above-mentioned 1. Second. Third
An even more stable ALC circuit can be obtained by using a control 1M signal generation circuit consisting of a plurality of signal level detection circuits, such as by combining the embodiments of the following.

〔Effect of the invention〕

As described above in detail, the ALC circuit of the present invention is as follows:
Instead of having multiple signal level detection circuits, it is equipped with a control signal generation circuit that can control the generation characteristics of the control signal for the output of the ALC circuit to the desired characteristics, so there is no need to worry about compromising stability like in the past. It is possible to provide a highly stable ALC circuit in which the level fluctuation of the output signal with respect to the input signal is small and the response time of the output signal to the level fluctuation of the input signal is short.The effect is great. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional ALC circuit, FIGS. 2 to 5 are diagrams for explaining the characteristics of the ALC circuit shown in FIG. 1, and FIG. 6 is a circuit diagram showing an example of a conventional ALC circuit. Circuit diagram, 7th
10 are diagrams for explaining the characteristics of the first embodiment of the present invention, FIG. 11 is a circuit diagram of the second embodiment of the present invention, and FIG. 12 shows all the characteristics of the second embodiment of the present invention. FIG. 13 is a circuit diagram of the third embodiment of the present invention, and FIG. 14 is a diagram for explaining the characteristics of the third embodiment. l...Input terminal, 2...Attenuation circuit, 3
・・・・・・Amplification circuit% 4, 6, 7, 9, 10, 12
．． 13... Signal level detection circuit, 5...
・Output terminal, 8, 11° 14... Control signal generation circuit s Q 5-Qll... Transistor, D
1~D7...Diode, R1~tt14...
...Resistor C~C15...Capacitor. ,・1, Ku゛, Agent Patent Attorney Susumu Uchihara 4 -) ゛・(・ Ward 1, 2, 4, 3, Ward 5, B, 1, ρ, Fijia- No. fZ ff1, % Figure 14

Claims (2)

[Claims] (1) (An attenuation circuit whose attenuation amount of the ff signal is controlled by a control signal, an amplifier circuit that amplifies the output signal of the attenuation circuit, and a plurality of circuits that detect the thickness of the output signal of the amplifier circuit. An automatic level control circuit comprising: a signal level detection circuit; and a control signal generation circuit that outputs the control signal No. 100. (2) A patent claim in which the threshold level of at least one signal level detection circuit among a plurality of signal level detection circuits is controlled by the output of at least one other No. 1h level detection circuit. The automatic level control circuit according to item (1). Claim (1) or (1) is controlled by the output of at least one signal level detection circuit.
The automatic level control circuit described in section 2).