JPS6033454U - 半導体装置の構造 - Google Patents

半導体装置の構造

Info

Publication number
JPS6033454U
JPS6033454U JP12601783U JP12601783U JPS6033454U JP S6033454 U JPS6033454 U JP S6033454U JP 12601783 U JP12601783 U JP 12601783U JP 12601783 U JP12601783 U JP 12601783U JP S6033454 U JPS6033454 U JP S6033454U
Authority
JP
Japan
Prior art keywords
rectangular
hole
semiconductor device
case
plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12601783U
Other languages
English (en)
Inventor
秀章 小林
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP12601783U priority Critical patent/JPS6033454U/ja
Publication of JPS6033454U publication Critical patent/JPS6033454U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案による半導体装置の構造を示す斜視図、
第２図は第１図の方形ケースのＡ−Ａ断面図、第３図は
方形ケースと角形プラグとの嵌合の状態を示す斜視図、
第４図は半導体装置の端子配列をバス形式にし、積み重
ねた構造を示す斜視図である。 １・・・半導体装置の方形ケース、２・・・角形貫通孔
、３・・・接触端子（接片）、４・・・プリント板。 第３図 −第４図

Claims (1)

    【実用新案登録請求の範囲】
  1. 集積回路を内蔵した方形ケースの周縁部に多数の角形貫
    通孔を設け、各角形貫通孔の内壁面に、前記集積回路よ
    り引き出された複数のリード線にそれぞれ接続された弾
    性部材の接片を設け、プリント基板上に、前記方向ケー
    スに設けられた角形貫通孔に対応した角形プラグを着脱
    可能に設け、前記角形貫通孔と角形プラグを嵌合させる
    ことにより方形ケースの端子と角形プラグとの電気接続
    を行なうことを特徴とする半導体装置の構造。
JP12601783U 1983-08-12 1983-08-12 半導体装置の構造 Pending JPS6033454U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12601783U JPS6033454U (ja) 1983-08-12 1983-08-12 半導体装置の構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12601783U JPS6033454U (ja) 1983-08-12 1983-08-12 半導体装置の構造

Publications (1)

Publication Number Publication Date
JPS6033454U true JPS6033454U (ja) 1985-03-07

Family

ID=30286690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12601783U Pending JPS6033454U (ja) 1983-08-12 1983-08-12 半導体装置の構造

Country Status (1)

Country Link
JP (1) JPS6033454U (ja)

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