JPS6032836B2 - Time base device for time interval measurement - Google Patents

Description

[Detailed Description of the Invention] When measuring time intervals such as rectangular waves in analog-to-digital converters and other various devices, a device is used that counts clock pulses that have passed through a gate circuit controlled by the rectangular waves. It is being

As is well known, in such a time interval measuring device, an error of ±1 count occurs, but by making measurements N times and calculating the average value, if the period of the clock pulse is T, the time interval can be calculated. The resolution of T/VN can be improved. However, this effect cannot be obtained when the clock pulse and the time interval to be measured have an integer ratio, or when the start time of the time interval and the clock pulse are synchronized. Furthermore, the above effect can certainly be obtained by applying random phase modulation using clock pulse white noise, etc., but this requires a circuit with unstable operation such as a phase modulator, so manufacturing adjustment is not easy. At the same time, there is also a high risk of failure. Therefore, the present invention attempts to reliably obtain the above-mentioned effects by using a digital circuit with stable operation. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, in which the multistage delay circuit S includes, for example, a pulse delay line having one tap (n is a positive integer) or a delay line using the propagation delay of a gate. A circuit comprising a clock pulse source Q,
If the period of the pulses applied from 1 to 1 is T, then clock pulses having a delay time difference of T/1 are sequentially sent out from each of the output terminals a, b, . . . , p.

In addition, a counter with a full scale of 1 is used to manipulate and count the output pulses of the clock pulse source Q2 using the NI, and applies the count signal to the latch circuit L, which also receives the output of the flip-flop circuit F. is added as a latch signal. This flip-flop circuit F is reset by a signal at terminal 1 via a differentiation capacitor C, and is set by an output pulse from a random pulse generator W. A square wave is added. The random pulse generator W is a pseudo-random pulse generator used for testing circuits, integrated circuits, communication devices, etc., which amplifies white noise voltage generated by a resistor or diode, slices it with an appropriate bell, and sends the output pulse. It is composed of a generator circuit, etc., and sends out pulses at an appropriate frequency at random time intervals. Furthermore, the output of the latch circuit L is applied to the decoder D,
A signal is sent out from one of the output terminals b', . . . p' corresponding to the count value of the counter NI. 1 AND gate circuit board, Ab...
The decoder D and the multistage delay circuit S are connected to each of Ap.
The outputs of each are added one by one.

Therefore, among the AND gate circuits, Ab, ..., Ap, the one corresponding to the count value of the counter NI is opened, and the clock pulse sent from the gate circuit passes through the OR gate circuit 0 to measure the time interval. The input gate circuit A of the counter NO is added. Since this gate circuit AO is controlled by the rectangular wave at terminal 1, the number of clock pulses that overlap with the rectangular wave is counted by the counter NO, and its time width is measured. In the above-mentioned apparatus, a rectangular wave signal whose time width t is to be measured is applied to the terminal 1, for example as shown in FIG. 2i.

Further, the random pulse generator W generates a pulse train having completely irregular time intervals as w, and the count value of the counter NI changes as q. The flip-flop circuit F is reset to green after the signal i and is set by the next random pulse generated. Therefore, a latch signal is added to the latch circuit L, as shown in FIG. The count values xl, x2, etc. of NI are captured by the latch circuit. The decoder D sends out signals from output terminals corresponding to the count values xl, x2, etc., and opens one of the AND gate circuit fields, Ab, . . . Ap. Therefore, the output states a, b, ...p of the multistage delay circuit S
A clock pulse is applied to the input gate circuit AO of the measurement counter NO from the terminal connected to the open gate circuit. That is, each time the time width t of each rectangular wave in the signal i is measured, the delay amount of the input clock pulse becomes the count value xl,
It changes in response to x2, etc. Moreover, the generation time of each pulse of the random pulse w cannot be predicted at all,
Since there is no correlation with the count value of the counter NI, there is no fear that the rise time of the rectangular wave signal i applied to the input gate circuit AO of the counter will be synchronized with the clock pulse, and each output terminal of the delay circuit The probability that a clock pulse sent out by a clock pulse will be captured is uniform. Therefore, by sequentially measuring the time width of each rectangular wave of the signal i and finding the average value, it is possible to reliably improve the resolution of time interval measurement to T/1 by increasing the number of measurements. Moreover, since the operation is performed by a digital circuit, there are no parts that require delicate adjustments, making it easy to manufacture and operating stably and reliably.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.
FIG. 3 is a waveform diagram for explaining the operation of the device shown in the figure. In the figure, Q1 and Q2 are clock pulse sources, S is a multi-stage delay circuit, D is a decoder, L is the latch circuit, N0,
NI is a counter, F is a flip-flop. W is a random pulse generator, 1 is an input terminal of a rectangular wave whose time width is to be measured, Aa, Ab...Ap and Ao are AND gate circuits, and 0 is an OR gate circuit. Gez ■ Ushio/a

Claims (1)

[Claims] 1. A counter that repeatedly counts clock pulses, a latch circuit to which the output signal of the counter is applied, and a latch circuit that uses a pulse generated at an arbitrary time before the start of the time interval as a latch signal for each time interval measurement. a random pulse generator that applies a plurality of delays to the clock pulse, a multistage delay circuit that applies multiple stages of delay with equal delay time differences to the clock pulse and sends out the delayed output of each stage from each of the plurality of output terminals, and the latch circuit. and a logic circuit that applies the clock pulse obtained from the output terminal of the multi-stage delay circuit corresponding to the output counter of the counter thus captured to the input gate circuit of the time interval measuring counter. Timebase device for time interval measurements.