JPS6032496A - Hybrid circuit - Google Patents

Abstract

PURPOSE:To miniaturize the circuit by making electrostatic capacity of a capacitor that constitutes a balancing circuit small. CONSTITUTION:The input terminal of an operational amplifier OP5 is connected to the receiving circuit 4WR of a four-wire circuit and output terminal of an operational amplifier OP6 is connected to a transmitting circuit 4WS and an operational amplifier OP7 having the same circuit configuration with negative feedback and positive feedback circuits of operational amplifiers OP1, OP2 that feed terminal equipment connected to a two-wire circuit 2W is connected to output terminal of the amplifier OP5. A balancing circuit Z of equivalent circuit configuration with terminal equipment side is connected to output terminal of the amplifier OP7. An operational amplifier circuit OP8 adds output of the circuit Z to input terminal of the amplifier OP6 and eliminates sneak signal component passed through the terminal equipment side. Values of resistances R21-R25 of the amplifier OP7 are made n times that of resistances R1-R5, R11-R15 of amplifiers OP1, OP2, and electrostatic capacity of the circuit Z is made 1/n.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a hybrid circuit that performs two-wire and four-wire conversion.

Prior Art and Problems A hybrid circuit that performs two-wire and four-wire conversion is used to connect a terminal device such as a telephone to an exchange. Such hybrid circuits are made up of semiconductor integrated fffiJ circuits and are miniaturized, and are used to supply power to terminal devices (B
) function, status monitoring such as call detection of 6Iij terminal equipment (S)
Since it is equipped with tffl function and hybrid (11) function, it is also called BSI (circuit).In this way, it has a configuration that includes various functions in addition to 2-wire 4-wire conversion, and is capable of receiving 4-wire lines. A configuration is provided to prevent signals from the line from going around to the transmission line and lines of the 4-line line.In other words, a balance circuit with a circuit configuration equivalent to that on the terminal device side is provided, and the signal voltage generated in the balance circuit is provided. This is to cancel the signal voltage that has leaked into the transmission line of the 4-wire line.

Since the capacitance on the terminal device side is about 2 .mu.F, a 2 .mu.F capacitor must be connected to the balance circuit as well, and since the capacitance is relatively large, there is a drawback that the device becomes large.

OBJECTS OF THE INVENTION An object of the present invention is to reduce the capacitance of a capacitor constituting a balance circuit, thereby achieving miniaturization.

Structure of the Invention The present invention comprises: a first operational amplifier having an input terminal connected to a receiving line of a four-wire line; a second operational amplifier having an output terminal connected to a transmitting line of a four-wire line; a third operational amplifier connected to the output terminal of the operational amplifier and having the same circuit configuration as a negative feedback and positive feedback circuit of the operational amplifier that supplies power to a terminal device connected to the two-line line; a balance circuit connected to the output terminal of the operational amplifier and having a circuit configuration equivalent to that on the terminal device side; and an output signal of the balance circuit is manually inputted to generate a signal for canceling the wraparound signal component that has passed through the terminal device side. a fourth operational amplifier which outputs the output and adds it to the second operational amplifier nj,
1! The resistance in the circuit configuration of the third operational amplifier is set to n times the resistance value of the resistance in the circuit configuration of the operational amplifier that supplies power to the first terminal device, and the electrostatic charge of the balance circuit is It is characterized in that the capacitance is 1/n of the capacitance on the terminal device side, and the actual hs ui+ will be explained in detail below.

Embodiment of the Invention FIG. 1 is a circuit diagram of a main part of an embodiment of the invention, where DFA is a differential amplifier, OPI to OP8 are operational amplifiers, and R1=R3.
5, 'Rz is the resistance, ZN is the impedance on the terminal device side, Z is the balance circuit, C1 is the capacitance on the terminal device side, L
PF is a low pass filter, l (PF is a bypass filter, A I) is an adder circuit, 2W is a 2-wire line, 4WR is a 4
B is the reference voltage for the receiving line of the line, the transmitting line for the 4-wire line if 4WS is used. Note that the circuit configuration of the monitoring function of the terminal device such as call detection is omitted from illustration. operational amplifier OP1,
O20 supplies power to the terminal device connected to the 2-wire line 2W, resistors R2 and R12 are negative 1-point return resistors, and resistors R4 and R14 are positive feedback resistors, For example, R2, R12, R5° I715 = 4, R3,
R13=5.0Ω, R4゜R14=100Ω, R6,R
7=20 and Ω, and R1 and R11=20 and Ω. Also, increase the calculation 'l'! M unit OP3 is for suppressing the common mode component of the 2-wire line 2W, and has reference voltage B and ILX; anti-R16,
The voltage difference between the voltage at the connection point of R17 and the voltage at the connection point of R17 is applied to the resistors R6 and R7.
via operational amplifier OP1. This is a negative feedback to OP2.

The signal from the receiving line 4WR of the 4-wire line is input to one input terminal of the first operational amplifier OP5 via a resistor RL8, and the output signal of the operational amplifier OP5 is input to the differential amplifier DFA via the adder circuit AD. The output signal of the operational amplifier OP5 is input to the third operational amplifier OP7 via the resistor R21.
is input to the 10 input terminals. The differential amplifier DFA outputs signals whose polarities are mutually inverted, and a resistor R1 is connected to the input terminals of the operational amplifiers OPI and OP2 that constitute the power supply function circuit.
, R11. Therefore, the signal from the receiving line 4WR is transferred to the operational amplifier OPI on the 2-wire line 2W.
, OP2, and is sent to a terminal device such as a telephone.

The signal from the 2-wire line 2W is sent to the arithmetic/width unit OP4 through the resistor R.
27, input via R2O, low pass filter LPF
, the DC component is added to the adder circuit AD, and the bypass filter II P F adds the AC component to the adder circuit AD and the second
The signal is inputted to one input terminal of the operational amplifier OP6 via a resistor R34. The output of this operational amplifier OP6 is sent to a four-wire transmission line 4WS. Also low pass filter LP
The supply current from the power supply function circuit is controlled in accordance with the level of the DC and AC components from F and the bypass filter HPF.

Further, the output signal of the operational amplifier OP7 is applied to a balance circuit Z, and the output of the balance circuit Z is applied to one input terminal of the fourth operational amplifier OP8 via a resistor R31.

Then, the output of the operational amplifier OP8 is applied to one input terminal of the second operational amplifier OP6 via a resistor R33. As a result, the loop signal component that has passed through the terminal device side is canceled out.

Also, the resistors R21 to R25 connected to the operational amplifier OP7 are the resistors R1 to R5 of the power supply function circuit or the resistors R11 to R25.
Corresponding to R15, resistor R3L is resistor R27 or resistor R
2B, and conventionally, the values of the corresponding resistances were the same, and therefore the capacitance of the balance circuit Z was also the same value as the capacitance C1 on the terminal device side. .

In the present invention, the capacitance of the balance circuit Z is reduced while the transfer characteristics remain the same, and for this purpose, the resistors R21 to R25 and R31 are replaced by the resistors R1 to R31 of the power supply circuit. R5 (R11 to R15) is multiplied by n,
The capacitance (2) of the balance circuit Z is set to 1/n.

In that case, the value of n is selected so that the values of the resistor R21 connected to the tenth input terminal of the operational amplifier OP7 and the resistor R31 connected to the one input terminal of the fourth operational amplifier OP8 do not become too large. Ru.

Also, instead of multiplying all of the resistors R21 to R25 and R31 by n, the value of resistor R23 connected to the output terminal of the operational amplifier OP7 is multiplied by n, and the capacitance of the balance circuit Z is It is also possible to multiply by 1/n. in this case,
Since the values of the resistors R21 and R31 do not become extremely large, it is possible to stably cancel out the signal components caused by the output of the operational amplifier OP8.

For example, as shown in FIG. 2, the balance circuit Z includes a resistor R4.
0, R41 and capacitor C2,
Connect the resistors R40 and R so that the DC resistance is 600Ω between the terminals.
A resistance value of 4.1 is selected, and the capacitor C2 is selected to be 1/n of the capacitance 1ci on the terminal device side.

Therefore, if the capacitance ICI is 2 μF, the balance circuit Z
The capacitance of the capacitor C2 is (2/n) μF, which allows for miniaturization.

As mentioned above, the message from the receiving line 4V/R is /1i
iW, amplifier OP5. Differential amplifier DFA, operational amplifier O
The signal is sent to the two-line line 2W via P1, passes through the terminal device side, loops through the operational amplifier OP4, bypass filter I-I P F, and operational amplifier OP6 to the transmission line 4WS, and the content of the call is transmitted to the transmission line 4WS. to become unclear,
It can be canceled by the output of operational amplifier OP8. In addition, the capacitance of the capacitor forming the balance circuit Z, which is equivalent to the terminal device side, can be reduced.

Effects of the Invention As described in 2, the present invention has the first operational amplifier OP5 whose input terminal is connected to the receiving line 4WR of the 4-wire line, and the output, l, and N4 terminals connected to the transmitting line 4WS of the 4-line line. negative feedback and positive feedback of operational amplifiers OPI and OP2 that are connected to the output terminal of the first operational amplifier OP5 and supply power to the terminal device connected to the two-wire line 2W. a third operational amplifier OP7 having the same circuit configuration as the circuit; a balance circuit Z connected to the output terminal of the third operational amplifier OP7 and having a circuit configuration equivalent to the terminal device side; The output of the balance circuit Z is added to the input terminal of the second operational amplifier OP6, and a fourth operational amplifier OP8 is provided for canceling the loop signal component that has passed through the terminal device side. Resistor R1 in the circuit configuration of operational amplifier OP1.01)2 that supplies power
−R5, R11 to R15, the value of the resistors R21 to R25 in the circuit configuration of the third operational amplifier ○P7 is multiplied by n, and the capacitance of the balance circuit Z is 1/n.
Since the capacitance of the balance circuit Z can be reduced, there is an advantage that the size can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a balance circuit. DFA is a differential amplifier, OPI to OP8 are operational amplifiers, R
1-R35, Rz is the resistance, 22 is the impedance on the terminal device side, Z is the balance circuit, ILCI is the capacitance on the terminal device side, LPF is the low-pass filter, HP F is the bypass filter, AD is the adder circuit, 2W is the 21M line , 4WR is the receiving (word line) of the 4-wire line, 4ws is the transmitting line of the 4-wire line,
It is B41 standard voltage 1 King. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Aitani and 1 other person

Claims (1)

[Claims] a first operational amplifier whose input terminal is connected to the receiving line of the 4-wire line; a second operational amplifier whose output terminal is connected to the transmitting line of the 4-wire line; and an output terminal of the first operational amplifier; a third /iti operational amplifier having the same circuit configuration as the negative feedback and positive feedback circuits of an operational amplifier that supplies power to a terminal device connected to the two-wire line; and an output of the third operational amplifier. A balance circuit connected to the terminal and having a circuit configuration equivalent to that on the terminal device side, and an output signal of the balance circuit is inputted and outputs a signal for canceling the wraparound signal component that has passed through the terminal device side. a fourth operational amplifier added to the second operational amplifier, and the resistance in the circuit configuration of the third operational amplifier is greater than the resistance in the circuit configuration of the operational amplifier that supplies power to the terminal device. A hybrid circuit characterized in that the resistance value of the balance circuit is set to n times the resistance value, and the capacitance of the balance circuit is set to 1/n of the capacitance on the terminal device side.