JPS603167A - Manufacture of semiconductor light-emitting diode - Google Patents

Manufacture of semiconductor light-emitting diode

Info

Publication number
JPS603167A
JPS603167A JP58111342A JP11134283A JPS603167A JP S603167 A JPS603167 A JP S603167A JP 58111342 A JP58111342 A JP 58111342A JP 11134283 A JP11134283 A JP 11134283A JP S603167 A JPS603167 A JP S603167A
Authority
JP
Japan
Prior art keywords
film
layer
ohmic contact
electrode
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58111342A
Other languages
Japanese (ja)
Inventor
Yoichi Isoda
磯田 陽一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58111342A priority Critical patent/JPS603167A/en
Publication of JPS603167A publication Critical patent/JPS603167A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004Devices characterised by their operation
    • H01L33/002Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To prevent a creeping to a back electrode of an Au plating liquid, and to obviate a contamination by previously coating an electrode with an opening for extracting beams formed on the back of a substrate with a ZnO film having small conductivity when an Au plated layer is formed on an electrode layer as an uppermost layer constituting a light-emitting diode. CONSTITUTION:An N type InP buffer layer 2, an InGaAsP active layer 3, a P type InP re-lade layer 4 and a P type InGaAsP cap layer 5 are laminated on an N type InP substrate 1 and grown in an epitaxial manner, and an SiO2 film 6 for constricting currents, a central section thereof has a striped shape, is formed on the layer 5. A P-side ohmic contact metal 7 is applied while burying the striped shape and an Au plated film 11 is formed on the metal 7, but a back N- side ohmic contact metal 8 with an opening 12 for extracting beams previously formed is coated beforehand with a ZnO film 10 having very small conductivity at that time. The film 10 is removed, and an antireflection film 9 consisting of an SiO2, etc. is applied to the removed section of the film 10.

Description

【発明の詳細な説明】 本発明は半導体発光ダイオードの製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor light emitting diode.

半導体発光ダイオードは、近年元通値等の用途に盛んに
用いられておシ、その特性向上のために種々の改良が行
われている。半導体発光ダイオードの中でも、面発光型
の発光ダイオードには、うし出力の向上のために、元出
力取シ出し側の窓表面に反射防止膜を設ける事が行われ
ている。また、その光出力取出し窓と反対側の表面に形
成されたオーミックコンダクト用電極を、素子の信頼性
向上の目的から、厚いAuメッキ膜によって被い、放熱
特性金高める工夫も行われている。従来、上述の様な、
反射防止膜とAuメッキ膜を備えた面発光ダイオード全
製造するに当っては、基板の上に複数の半導体層(活性
層等)全成長させて多層半導体ウェハー(以後ウェハー
という)全形成した後に、そのウェハーの半導体層成長
111jの面(以後ウェハー表面という)に電流狭窄得
造を持ったオーミックコンタクト部全設け1次にウェハ
ーの前記表面に対面する面(以後ウニ/’%−裏面と呼
ぶ)の研摩によシ基板金薄くしてから、光出力取出し窓
?有するオーミックコンタクト電極と反射防止膜全形成
し、それに続いてウェハー表面に放熱効果?向上させる
ためのAuメッキMk設ける工程が行われている。Au
メッキ工程が最後に行われるのは、ウェハー裏面にオー
ミックコンタクト電極を設けるために必要な熱処理時に
、厚いAuメッキ層によって生ずるストレスやAuとウ
エノ・−との反応による合金化を避けるためという意味
があるとともに、Auメッキ膜’kVする薄く研摩され
たウェハーは反応が大きいので、電極バ開け、反射防止
膜バターニングのためのフォトレジスト工程においてウ
ェハー全薄板のガラス等に貼9つける事が困難になるか
らである。しかしながら、従来の様なAuメッキ工程全
最後に行う方法を採っても、次に述べる様な欠点がある
。Auメッキ工程においては、薄片化されたウエノ・−
の帖面全フォトレジスト等金用いて支持用のガラス板に
貼りつけた状態でメッキ葡行うが、メッキしている間に
ウェハーが次第に反ってきて、ウェハー裏面とガラス板
との間ではがれ盆生じウェハー裏面へAuメンキ液が回
シこんで電極表面を汚すという問題が生ずる。このよう
な汚れが生ずると外観が損われるばかシでなく、リード
線を設けるときに、その付着力が大きく低下する。
Semiconductor light emitting diodes have been widely used in recent years for applications such as excitation, and various improvements have been made to improve their characteristics. Among semiconductor light emitting diodes, surface emitting type light emitting diodes are provided with an anti-reflection film on the window surface on the main output side in order to improve the output power. Furthermore, for the purpose of improving the reliability of the device, an attempt has been made to cover the ohmic conductive electrode formed on the surface opposite to the light output extraction window with a thick Au plating film to improve the heat dissipation properties. Conventionally, as mentioned above,
To fully manufacture a surface emitting diode equipped with an anti-reflection film and an Au plating film, multiple semiconductor layers (active layers, etc.) are fully grown on the substrate, and a multilayer semiconductor wafer (hereinafter referred to as wafer) is fully formed. , all ohmic contact portions with current confinement are provided on the surface of the semiconductor layer growth 111j of the wafer (hereinafter referred to as the wafer surface).First, the surface facing the front surface of the wafer (hereinafter referred to as the back surface) is provided. ) After polishing the substrate to make it thinner, remove the light output window? Is the ohmic contact electrode and anti-reflection film fully formed, followed by a heat dissipation effect on the wafer surface? A process of providing Au plating Mk is being carried out to improve the quality. Au
The reason why the plating process is performed last is to avoid stress caused by the thick Au plating layer and alloying due to the reaction between Au and Ueno during the heat treatment required to provide ohmic contact electrodes on the back side of the wafer. At the same time, a thinly polished wafer with an Au plating film of 'kV' has a large reaction, so it is difficult to attach it to glass, etc. of the entire wafer in the photoresist process for opening the electrode bar and buttering the anti-reflection film. Because it will be. However, even if the conventional method of performing Au plating at the end of the entire process is adopted, there are drawbacks as described below. In the Au plating process, thinned Ueno-
Plating is carried out with the whole surface of the wafer pasted on a glass plate for support using photoresist, etc., but during plating the wafer gradually warps, and a peeling tray occurs between the back side of the wafer and the glass plate. A problem arises in that the Au coating liquid flows back onto the back surface of the wafer and contaminates the electrode surface. When such stains occur, not only does the appearance deteriorate, but also the adhesion force when installing lead wires is greatly reduced.

本発明の目的は、Auメッキ工程において、光出力取出
し窓側のオーミックコンタクト用電極がAuメッキ液に
よる汚染上受は難い半導体発光ダイオードの製造方法の
提供にある。
An object of the present invention is to provide a method for manufacturing a semiconductor light emitting diode in which the ohmic contact electrode on the side of the light output extraction window is not easily contaminated by the Au plating solution during the Au plating process.

本発明による半導体発光ダイオードの製造方法は、活性
層?含む複数の半導体層上基板上に成長させて多層半導
体ウェハー全形成する工程と、この多13半導体ウェハ
ーの前記半導体層成長側の第1の表面に電流狭窄構造の
第1のオーミック電極全形成する工程と、前記多層半導
体ウニ・・−の前記第1の表面に対面するa)↓2衣面
に元出力取シ出し用の開口がある第2のオーミック電極
全形成する工程と、前記開口を覆う反射防止膜全形成す
る工程と、前記第2のオーミック?’b、K及び前記反
射防止膜會覆りZnO膜?形成する工程と、このZnO
膜形成の後に前記第1のオーミック電接上にAuメッキ
奮施す工程と、このAuメッキ工程の後に前記ZnO膜
を除去すの工程と金含んで構成される。
The method for manufacturing a semiconductor light emitting diode according to the present invention includes an active layer? a step of fully forming a multilayer semiconductor wafer by growing a plurality of semiconductor layers on a substrate, and fully forming a first ohmic electrode with a current confinement structure on a first surface of the semiconductor wafer on the semiconductor layer growth side; a step of completely forming a second ohmic electrode having an opening for taking out the original output on the a)↓2 surface facing the first surface of the multilayer semiconductor urchin; The process of completely forming the covering anti-reflection film and the second ohmic film? 'b, K and the ZnO film covering the anti-reflection film? The process of forming and this ZnO
The method includes a step of plating Au on the first ohmic contact after film formation, and a step of removing the ZnO film after the Au plating step.

次に図面全参照して本発明の詳細な説明する。The present invention will now be described in detail with reference to all the drawings.

第1図1、a)〜(h)は、それぞれ本発明の一実施例
の中間工程における半製品の断面図である。本実施例に
おいて用いられる基板lはn型InPである。
FIGS. 1A to 1H are cross-sectional views of semi-finished products in intermediate steps according to an embodiment of the present invention. The substrate l used in this example is n-type InP.

本図ta)は、n型InP基板1の上に連続エピタキシ
ャル成長によシ、n型InPバッファ一層2゜InGa
AsP活性層3.P型IrKPクラッド層4゜p型In
GaAs’Pキャップ層5紫成長させて形成したウェハ
ー金示す。第1図(b)は、本図(a)のダブルへテロ
構造ウェハーの表面のp型InGaAsPキャップ層5
上に電流狭富用の5iOz等よシ成る絶縁膜6全形成し
た後、フォトレジスト工程によシ開ロ部金設けた半製品
金示す。同図(C)は、bi40ケ有する絶縁膜6の上
に、p側オーミック接触金属7’!i:被着させた後、
熱処理してオーミック接触奮得た半製品上水す。同図(
dJは% InP基板l?研摩した後、n側オーミック
接触金属8ケ被着せしめてからフォトレジスト工程によ
9元取り出し用開口12會設け、続いて熱処理を行い、
n側のオーミック接触?得た中間製品上水す。同図(e
)は、元取シ出し用開口12に、プラズマCVDあるい
はスパッタリング等により、SiNx、5i02等の反
射防止膜9全被着せしめた後、フォトレジスト工程に、
lニジバターニングした中間製品を示す。同図(f)は
、スパッタリングにより厚さ0.5〜1μm程度のZn
O膜10e、n側オーミック接触金属8及び反射防止膜
9の上に被着せしめた半製品を示し、このZnO膜1膜
設0設工程に本発明の犬@な特徴がある。同図(g)は
、フォトレジスト等によシZnO膜10の側音ガラス板
等の支持体に貼シ付けた後、フォトレジスト工程を用い
てp側オーミック接触金属7の上にAuメッキ膜11?
選択的に設けた半製品?示す。このAuメッキ工程にお
いては、nuljオーミック接触金属8の上に導1δ性
の非常に小さいZnO膜IOが被着されているだめに、
従来の製造方法で生じていたAuメッキ液の回シこみに
よって生ずるn側オーミック接触金属8辰面の汚れが避
けられる。本図(h)は、ZnO膜10が純水希釈のa
度1%程度の室温希リン酸液に極めて各易に溶解ijJ
能である特徴ケ利用して、ZnO膜10金除去した半製
品ケ示す。
In this figure (ta), an n-type InP buffer layer of 2° InGa is formed by continuous epitaxial growth on an n-type InP substrate 1.
AsP active layer 3. P-type IrKP cladding layer 4°p-type In
The GaAs'P cap layer 5 is shown grown on a wafer gold. FIG. 1(b) shows the p-type InGaAsP cap layer 5 on the surface of the double heterostructure wafer shown in FIG. 1(a).
After an insulating film 6 made of 5 iOz or the like for current narrowing is completely formed on top, a semi-finished metal is shown in which an opening metal is provided by a photoresist process. In the same figure (C), a p-side ohmic contact metal 7'! i: After being deposited,
Semi-finished tap water that has been heat treated to achieve ohmic contact. Same figure (
dJ is % InP substrate l? After polishing, 8 n-side ohmic contact metals were deposited, and 12 openings for taking out the 9 elements were formed using a photoresist process, followed by heat treatment.
Ohmic contact on the n side? The intermediate product obtained is tap water. The same figure (e
), the anti-reflection film 9 of SiNx, 5i02, etc. is completely deposited on the opening 12 for removal by plasma CVD or sputtering, and then subjected to a photoresist process.
1 shows an intermediate product that has been subjected to rainbow butterning. In the same figure (f), Zn with a thickness of about 0.5 to 1 μm is deposited by sputtering.
A semi-finished product is shown in which the ZnO film 10e, the n-side ohmic contact metal 8 and the anti-reflection film 9 are coated, and the unique feature of the present invention lies in the step of forming one ZnO film. In the same figure (g), after pasting the ZnO film 10 on a support such as a sidetone glass plate using photoresist or the like, an Au plating film is applied on the p-side ohmic contact metal 7 using a photoresist process. 11?
Selectively provided semi-finished products? show. In this Au plating process, since a very small ZnO film IO with 1δ conductivity is deposited on the nulj ohmic contact metal 8,
It is possible to avoid contamination of the n-side ohmic contact metal 8 shin surface caused by the Au plating solution being squeezed in in the conventional manufacturing method. In this figure (h), the ZnO film 10 is diluted with pure water.
Very easily dissolved in dilute phosphoric acid solution at room temperature of about 1%
A semi-finished product from which gold has been removed from a ZnO film is shown below.

00時5iiNx、5i02等よりなる反射防止膜9は
浸されない(このZnO膜の除去処理については、技術
論文集[Digest of Tech、Papers
The 8th Conf−(1976Interna
tional)ovx 5olid 5tate De
vices、 Tokyo;43−6−21及び特願昭
50−124930に詳述しである)。
At 00:00, the antireflection film 9 made of 5iiNx, 5i02, etc. is not immersed.
The 8th Conf-(1976Interna
tional) ovx 5olid 5tate De
vices, Tokyo; 43-6-21 and Japanese Patent Application No. 124930/1980).

b<i図(h)の半製品は、素子分離やリード線取付は
等の工程會経てInPを基板とする面発光をの発覚ダイ
オードとして完11y、する。
The semi-finished product in Fig. b<i (h) is completed as a surface-emitting detection diode using InP as a substrate through processes such as element separation and lead wire attachment.

上述の様に、本発明に基づくならば、従来の面発元型の
半導体発光ダイオードの製造方法ケ使用したときには放
熱用のAuメッキ脱形成時にしばしば生じていたメッキ
膜全形成しない側の面に設けられた電極のメッキ液によ
る汚れが大幅に低減され、素子としての外LQt損わず
に爵むとともに、リード線の付着力を強固にできるとい
う長所が生ずる。また、前記実施例ではInPケ基板と
する場合全掲げたが、GaAs、GaP等の他の材料の
基板を用いて面発元型の発う゛Cダイオードk X’L
造する場合にも、本発明は適用できる。
As described above, based on the present invention, when using the conventional manufacturing method of surface-emitting type semiconductor light emitting diodes, the plated film, which often occurs when removing the Au plating for heat dissipation, is removed from the surface on which the entire plating film is not formed. Contamination of the provided electrodes by the plating solution is greatly reduced, the external LQt of the device is not damaged, and the adhesion of the lead wires can be strengthened. In addition, in the above embodiments, all cases are shown when using an InP substrate, but a surface-emitting type diode k
The present invention is also applicable to the case of manufacturing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(h)は、本発明の一実施例における各
中間工程の半製品葡それぞれ示す断面図である。 1・・・・・・n型InP基板、2・・・・・・n型I
nPバッファ一層、計・・・・・InGaAsP活性層
、4・・・・・・p堅1 n Pクラッド層、5・・・
・・・p型InGaAsPキャップ層、6・・・・・・
絶縁膜、7・・・・・・p 9(11オーミツク接触金
属、8・・・・・・n側オーミック接触金#b9・・・
・・・反射防止膜、10・・・・・・ZnO膜、11・
・・・・・Auメッキ膜、12・・・・・・元取シ出し
用開口。 代理人f1理士内j京 晋 。 (t2.ン IC) 、〆。 早 1
FIGS. 1(a) to 1(h) are cross-sectional views showing semifinished grapes in each intermediate step in an embodiment of the present invention. 1...n-type InP substrate, 2...n-type I
One layer of nP buffer, total... InGaAsP active layer, 4... p-type 1 nP cladding layer, 5...
...p-type InGaAsP cap layer, 6...
Insulating film, 7...p 9 (11 ohmic contact metal, 8...n side ohmic contact gold #b9...
...Antireflection film, 10...ZnO film, 11.
...Au plating film, 12...Original removal opening. Agent f1 Rishinai J Kyo Susumu. (t2.n IC), 〆. Early 1

Claims (1)

【特許請求の範囲】[Claims] 活性層を含む複数の半導体層全基板上に成長させて多層
半導体ウェハーを形成する工程と、この多層半導体ウェ
ハーの前記半導体層成長側の第1の表面に7暇流狭窄構
造の第1のオーミック電極上形成する工程と、前記多層
半与体ウェハーの前記第1の表面に対面する第2の表面
に元出力取シ出し用の開口がある/第2のオーミック電
極を形成する工程と、前記開口上積う反射防止膜を形成
する工程と、前記第2のオーミック電極及び前記反射防
止膜を覆うZnO膜を形成する工程と、このZnO膜形
成の後に前記第1のオーミック電極上にAuメッキ金施
す工程と、このノヘUメソキ工程の後に前記ZnO膜を
除去する工程と金含む半導体発光ダイオードの製造方法
forming a multilayer semiconductor wafer by growing a plurality of semiconductor layers including an active layer all over the substrate; a second ohmic electrode having an opening for taking out the original output on a second surface of the multilayer semi-donor wafer facing the first surface; a step of forming an anti-reflection film overlying the opening; a step of forming a ZnO film covering the second ohmic electrode and the anti-reflection film; and after forming the ZnO film, plating Au on the first ohmic electrode. A method for manufacturing a semiconductor light emitting diode containing gold, including a step of applying gold, a step of removing the ZnO film after the metallization step.
JP58111342A 1983-06-21 1983-06-21 Manufacture of semiconductor light-emitting diode Pending JPS603167A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58111342A JPS603167A (en) 1983-06-21 1983-06-21 Manufacture of semiconductor light-emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58111342A JPS603167A (en) 1983-06-21 1983-06-21 Manufacture of semiconductor light-emitting diode

Publications (1)

Publication Number Publication Date
JPS603167A true JPS603167A (en) 1985-01-09

Family

ID=14558760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58111342A Pending JPS603167A (en) 1983-06-21 1983-06-21 Manufacture of semiconductor light-emitting diode

Country Status (1)

Country Link
JP (1) JPS603167A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02213175A (en) * 1989-02-14 1990-08-24 Matsushita Electric Ind Co Ltd Light-emitting semiconductor device
CN105679896A (en) * 2016-03-28 2016-06-15 扬州乾照光电有限公司 Gallium arsenide-based low-brightness yellow light-emitting diode chip and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02213175A (en) * 1989-02-14 1990-08-24 Matsushita Electric Ind Co Ltd Light-emitting semiconductor device
CN105679896A (en) * 2016-03-28 2016-06-15 扬州乾照光电有限公司 Gallium arsenide-based low-brightness yellow light-emitting diode chip and manufacturing method thereof

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