JPS603136A - Formation of wiring - Google Patents

Abstract

PURPOSE:To make gently the inclination of the edge part of a wiring, and to improve step coverage of an insulating film and the wiring by a method wherein a groove is formed in the first insulating film, and after the first wiring is formed in the groove part thereof, a second insulating film and a second wiring are laminated to be formed. CONSTITUTION:A first insulating film 2 is provided on a semiconductor substrate 1, and the resist pattern of the desired wiring shape is formed according to a first resist 3 on the film 2 thereof. Then wet etching is performed to the film 2 using the resist 3 as a mask to form a groove 4. At this time, side etching is performed to the edge part of the groove 4 to form a circular arc type. After the resist 3 is removed, a metal layer 5 is provided on the whole surface of the substrate 1, and the pattern of a second resist 6 is formed on the layer 5. At this time, pattern width of the resist 6 is enlarged than pattern width of the resist 3. Then wet etching is performed to the layer 5 using the resist 6 as a mask to form a first wiring 7. Then the resist 6 is removed, a second insulating film 9 is provided, and when a second wiring 10 is formed on the film 9, the film 9 and the wiring 10 are formed having favorable step coverage.

Description

DETAILED DESCRIPTION OF THE INVENTION A) Field of Industrial Application The present invention relates to a method for forming wiring, particularly to a method for forming wiring formed in multiple layers.

(Example) Conventional technology As the degree of integration of semiconductor devices increases, multilayer wiring technology becomes more important. However, when multilayer wiring (for example, AJ 2-layer, 3-layer wiring) is performed using conventional semiconductor processes,
The higher the upper layer≦2, the larger the base level difference becomes, leading to problems such as poor step coverage of the interlayer insulating film and wiring metal.

C) Purpose of the Invention The present invention has been developed in view of the above point C. In addition to reducing the level difference in the wiring part, the slope of the side surface of the wiring is gentle C2, and further layers are stacked on top of the wiring. The purpose of the present invention is to provide the same level of insulation film and wiring as described above.

2) Structure of the Invention The present invention comprises a step of providing a first resist on a first insulating film on a substrate, performing etching using the resist as a mask, and forming a groove in the first insulating film C: a desired wiring shape. After forming a metal layer on the entire surface of the substrate including this groove, a second resist having a wider pattern width is provided on the metal layer in the groove part (C2). The metal layer is etched using the resist No. 2 as a mask to form a first wiring in the groove, and a second insulating film and a second insulating film are formed on the substrate including the first wiring.
The process consists of a step of forming interconnects in a layered manner.

e) Embodiment FIGS. 1 to 5 are cross-sectional views showing the wiring forming method of the present invention in the order of steps, and the present invention will be explained in detail using these figures. First, a semiconductor substrate (8 on 11) made of silicon etc.
A first insulating film (2) made of 102 or the like is provided, and this first insulating film (2) is
A resist pattern having a desired wiring shape is formed using a first resist (3) on the insulating film (2) (FIG. 1). Next, using this first resist (3) as a mask, the first insulating film (2
) is etched using a hydrofluoric acid etchant, and grooves (4) are formed in the desired wiring shape to a depth of 1, for example.
It forms to a degree of ooou (Fig. 2). At this time, the groove (
4) The end portion is side-etched to form a circular arc (2). After removing the first resist (3), the substrate including the groove (4) (11 entire surface C: vapor deposition method C; metal made of AJ etc. A layer (5) with a thickness of about 200 OA is provided, and a second resin having the same pattern as the groove (4) is placed on the metal layer (5) on the groove (4).
(61 is formed (Fig. 3). At this time, the resist pattern width of the second resist (6) is set to be larger than the pattern width of the first resist (3) when forming the groove (4). The width of this second resist (6) is the groove (4).
It is best to set it to a medium level. Next, apply this second resist (6
) was used as a mask to wet-etch the metal layer (5) using a phosphoric acid-based etchant to form the groove (4).
A first wiring (7) is formed which is half-buried in the (FIG. 4).

At this time, the slope of the end (8) of the first wiring (7) is also gentle (2).Then, the second resist (6) is removed and the second insulating layer made of 5i02 is formed using the OVD method. Membrane (9
), and furthermore, when a second wiring (1α) consisting of C2AJ is formed on this second insulating film (9), these second wirings (7
) The insulating film (9) and the second wiring a■ are the first wiring (7)
The step coverage is also good at the intersection with (FIG. 5).

Figure 6 shows a multilayer interconnect using the present invention when there is a step under the first insulating film (2) (second lower layer interconnect (11), etc.). Also, the first wiring (the number where the slope of the end (8) of 71 is gentle),
The step coverage of the second insulating film (9) and the second wiring (Il) can be improved.

F) Effects of the Invention As described above, the wiring forming method of the present invention provides the first wiring formation method.
Since the insulating film and the second wiring are laminated, the step caused by the first wiring becomes small, and the slope of the end of the first wiring becomes acidic, so that the second insulating film and the second wiring The step coverage is improved, and reliability can be improved in multilayer wiring ≦2.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views showing the process order C2 of the wiring method of the present invention, and FIG. 6 is a cross-sectional view showing another example multilayer wiring structure formed using the method of the present invention. (])...Substrate, (2)(91...Insulating film, (
31 (61...resist, (7) (1ω...wiring). Applicant SANYO Electric Co., Ltd.

Claims (1)

[Claims] 1) On a semiconductor substrate (when forming a multilayer wiring, a first insulating film is provided on the substrate, and a first insulating film is provided on the first insulating film.
Forming a turn with a resist pattern of the desired wiring shape, and etching the surface of the first insulating film using the resin pattern as a mask. After forming a metal layer on the entire surface of the substrate, a pattern "I" is formed on the metal layer in the groove part 1: wider than the resist pattern width for opening the groove by the first resist 1-.
A second resist is provided to nail the pattern of J, and this second resist is
The metal layer is etched using the resist as a mask, and the metal layer is left in the groove to form the first wiring, and then a second insulating film is formed on the entire surface of the substrate by the OVD method. ≦-1 A wiring forming method in which a second wiring having a desired shape is formed on this @2 insulating film.