JPS603135A - Semiconductor memory circuit device - Google Patents

Abstract

PURPOSE:To enable to execute simply the test of a semiconductor memory circuit device without using an expensive and complicated tester by a method wherein the circuit having a test faculty is built in the memory circuit chip. CONSTITUTION:When an oscillating condition signal is selected by an input terminal 5, a self oscillating circuit 1 outputs a signal from a first signal terminal S1. The output terminals Q0-Qn-1 of a binary counter circuit 2 to count the output signals of the circuit 1 thereof output signals respectively, and a memory circuit 3 is addressed according to the signals thereof. Moreover the circuit 3 can select respectively a writable condition and a readable condition accordint to the signal of an input terminal 8. When the condition of the terminal 8 is in the writable condition, the second signal terminal S2 of the circuit 1 outputs a signal necessary for writing, and the data signal of an input terminal 7 is written to the circuit 3. Moreover, when the condition of the terminal 8 is in the readable condition, the output signal of the terminal D0 of the circuit 3 and the input signal of the terminal 7 are sent to a correct and erroneous action judging circuit 4, and signals corresponding respectively to normal action and erroneous action are outputted from an output terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit device, and in particular, generates an address signal and a read/write signal using a self-oscillation circuit and a binary counter circuit provided in the circuit, and further compares the output with an expected value. The present invention relates to a semiconductor memory circuit device that is equipped with a correct/false operation determination circuit, thereby making it possible to easily determine whether the circuit operates correctly or incorrectly without using an expensive and complicated test device.

Recently, with the increase in the scale of integrated circuits, the test equipment used to test the circuits has become more expensive and complex.Also, the increase in the number of internal elements of integrated circuits reduces the time it takes to create test programs. In addition, with regard to wafer inspection of integrated circuits, the time required to measure defective chips becomes longer due to the decrease in yield due to higher integration. All this results in an increase in the cost of testing in the cost of integrated circuits per chip. Therefore, it is extremely important to test integrated circuits at low cost and easily. The significance of this really lies in this point.

The present invention has a built-in circuit with a test function in the memory circuit chip, so it has the advantage that circuit tests can be easily performed without using expensive and complicated test equipment.・Wafer inspection, where there are relatively many defective chips, requires expensive and complicated test equipment (・(・), so it is particularly effective in reducing testing costs. Also, during the product development stage, Since it is easy to test, it is possible to easily test for problems in the trial production process, and the present invention is effective even in this case.

The present invention will be described in detail below with reference to the drawings.To make the explanation easier to understand, the memory circuit is a static memory (S).
RAM). A conventional semiconductor memory circuit is widely known as follows: 11 memory cells 11 for storing information, a read/write circuit 11 for reading and writing information (read/write), and a "read/write circuit 11" for determining the storage location (address) of information. !1 address circuit 1 and does not have a circuit with a test function (・Therefore, an expensive and complicated test device called a memory tester was required to determine whether the circuit operates correctly or incorrectly.

FIG. 1 is a diagram explaining the basic configuration of the present invention, and FIG. 2 shows signals of each circuit section to explain the operation of FIG. 1.

First, the basic principle of the present invention will be explained using FIG. In this figure, the self-oscillation circuit 1 is configured so that the self-oscillation circuit's ``oscillation state'' and ``oscillation stop state 1'' can be selected by the signal at the input terminal 5.The δ binary counter circuit 2 is a self-oscillation circuit. This is a circuit that counts the oscillation signals of 1 and outputs the counted value as a binary signal to multiple output terminals of the circuit. 3 is the same as a conventional semiconductor memory circuit, and includes a memory cell, an AT 71 circuit, and a read/write circuit. The output ID of the binary counter circuit 2, which is a memory circuit having a circuit, is connected to the address signal input of the memory circuit 3. 4 is a positive signal that determines whether the memory circuit 3 is operating correctly. By comparing the output signal of the storage circuit which is a malfunction determination circuit and the data input signal 7, it outputs a correct/incorrect judgment (L number) corresponding to correct or incorrect operation from output 1>ili' output 6.

Also, one signal in the self-oscillation circuit 1 is used as a write or read signal for the WEj circuit 3.

In the circuit shown in Fig. 1 which consists of (A) on IJ, when the signal in the 11 oscillation state II is selected at the input terminal 5, the self-oscillation circuit outputs the first signal as shown in the second fiQS1. (The oscillation frequency is determined by the characteristics of the self-oscillation circuit and can be freely designed.) Outputs 01, 0□, 02 of the binary counter circuit that calculates the output signal of the self-oscillation circuit
・・・・・・0o and Oo (Ao) in Figure 2 respectively
, 0+ (A-1)+02 (-A2) +On-+(
An-+) are outputted and transmitted to the address signal input of the memory circuit section, and the memory circuit is addressed by the signals. On the other hand, the signal S2 of jg2 output from the self-oscillation circuit can output a necessary force signal for writing into the memory circuit, or output an unnecessary signal for reading, depending on the input signal No. 41 of child 8. As shown in FIG. If the state of input terminal 8 F5 is in the omissible state, c'l: S
The signal No. 2 outputs a signal that is required to be read into each of the memory cells selected by the address signal from the binary counter circuit. Also, when the input terminal 8 is in the starting state, the signal S2 outputs the signal necessary for reading, and the output signal Do of the storage circuit and the data input signal of the input terminal 7 (in the reading, starting state) are output. (inputs an expected value signal) is sent to a correct/correct operation determining circuit, and outputs signals corresponding to normal operation and V1υ operation from the output terminal 6.

Note that the signal at input terminal 8 is sent to the correct/malfunction judgment circuit (also sent to the correct/malfunction judgment circuit, and only when the signal at input terminal 8 selects the v-extrusion state does the correct/malfunction judgment circuit 1, correct/malfunction judgment occur). Make sure that it is removed.

FIG. 3 is an example of the central feature of the present invention. 3rd below
The coffin shown in the figure, and the 4th work, are clearly clarified.

In Figure 3, A N D gate Gl, impark gate ()
2゜Ci 3, G4, and G5 are connected in series to form G5.
The output of G1 is fed back to the input of G1 to form a self-oscillating circuit rV+.The input terminal 301 is the input terminal B for controlling the oscillation state 0 and n oscillation stop state +1 of the self-oscillation circuit. A high level signal inputs the 11 oscillation state I+, and a low level signal indicates the "excavation stop state" 7.The signal at the input terminal 301 is also input to the binary counter circuit BC, and the input signal is set to a low level. By doing so, all outputs of the binary counter (iBC) are forced to a high level.

The first oscillation output terminal 304 of the self-oscillation circuit is connected to the binary counter circuit BCcF-1 number input terminal, and the oscillation signal of the self-oscillation circuit is counted in binary numbers to the binary counter PgBC to obtain the one-way value. Output terminal A0', A,
',...''rl-svc output. Output A of binary counter circuit BC.l ``4'l...''
...9A'11-1 are AND gates GAo respectively
, GAl, ...= Input to GA n s and output of the gate (': t is the main %Q f, α
+, :; ke, address input terminal A of the IC. , A1.・
..., connected to Ar1-□ (・ru.

The second oscillation output of the self-oscillation circuit is an exclusive or exclusive output of gates G2 and G4 that constitute the furnace circuit.
The output of the exclusive OR gate G6 is connected to the read/write signal input WE of the main memory circuit MC through a NAND gate G7 and an AND gate G8, and also constitutes a correct/malfunction determination circuit CC to be described later. Game) Input to CG2. The correct/malfunction judgment circuit CC includes an exclusive OR gate CGI and an A-NG gate CG.
2. Inverter game) The CG 3 and flip-flop circuit are constructed as shown within the broken line in FIG. In other words, exclusion or game) CGI is the output DO of the main memory circuit section and the omitted data/expected value data signal input terminal DI.
It works to detect the match/mismatch of the signals, and inputs the match/mismatch signal to the AND game (CG2). Also, the AND game)
The second oscillation output of the above-mentioned self-oscillation circuit is input to another input of CG2, and only when this signal is at a high level, the match/mismatch signal of CG1 is sent to the clock input terminal of the next-stage flip-flop circuit. As if sent to CLK (・
Ru.

On the other hand, the input of CG3 (inverter game) is input Inui 1 child 307
The output of the inverter game) CG3 is sent to the clear terminal CLR of the above-mentioned flip-flop circuit (.
Ru. In addition to the aforementioned clock input terminal and clear terminal CLR, the flip-flop circuit has seven flip-flop data input terminals as input signal terminals, and these flip-flop data input terminals are grounded. On the other hand, the output terminal Q of the flip-flop circuit is a normal/malfunction determination signal output terminal 306.

Input signal terminals CS and WE' in Figure 3.

Ao", A,"...A! 'n, . . . are external terminals used when the memory circuit is in use, and are kept at a high level during a test to determine whether the output circuit is operating correctly or incorrectly.

The operation of the circuit shown in FIG. 3 according to the present invention having the above configuration will be described below. When the input 301 is at a high level (・te,
The self-oscillating circuit is in an oscillating state, and the binary counter circuit is in a phantom counting operation state. Therefore, an address scan is performed according to the address input of the main memory circuit MC (or the output of the binary counter circuit).On the other hand, by keeping the input terminal 307 at a high level, the self-oscillation signal generated by the oscillation circuit is The input signal is sent to the main memory circuit MC through G7 and G8. In this state, the data input terminal DI
The signal is written to the main memory circuit section. If the data input signal is kept at a constant level, the data input signal will be written to all memory cells after scanning all memory cells. Since the terminal 307 is kept at a high level, a low level is input to the clear terminal CL of the flip-flop circuit in the correct/malfunction judgment circuit section, and the output Q of the flip-flop circuit is stingy, and the correct/malfunction judgment terminal 306 (
When the input terminal 307 is set to a low level after writing is completed, the input signal WEI''i of the main memory circuit section remains high and the level of the memory cell selected by the address circuit remains constant. The content is output to the output terminal 1)o. (・This is the so-called reader output state.) In this state, the input terminal 301 +1'j goes to a high level and becomes 1b. The oscillation circuit is in an oscillation state, and therefore the address is in a scan state.The main source (output 1 if the Q circuit section is operating normally)oi is outputting the data signal that was input before (( The correct/malfunction judgment circuit compares it with the input data signal (the 1 set of signals).The correct/malfunction judgment circuit section compares the output of the output circuit with If the address is input to the exclusive OR circuit and the above two signals match in all memory cells during all cell scanning (singing in normal operation), the circuit CGl
The output of is kept low at 1δ. Therefore, the clock signal CLK of the next-stage 7 lip-flop circuit is kept at a low level of 1/bell, and the flip-flop data that is grounded is slid into the flip-flop ladle. It remains at a high level. While the address is being scanned for all cells, - times or multiple times in the main memory "If there is a mismatch between the output DO of the 1st path and the expected value, it is a mismatch! (When there is one malfunction) Correct/Malfunction The output device level of the exclusive OR gate CGh in the judgment circuit section
4) Through the gate CG2, the clock terminal CLK of the next stage amplifier is set to high level. Since ground data is written in this clock-n-rip-n-lop, the correct/malfunction determination output 306 maintains this state at a low level. Therefore, by preventing whether the normal/malfunction determination output terminal is at a high level or a low level, it is possible to very easily test whether the memory circuit chip is operating normally or malfunctioning.

As described above, if the present invention is implemented, the test can be easily performed with a simple test device at low cost without using expensive and complicated test equipment, and without requiring a professional test equipment user. There are many extremely effective aspects, such as being able to reduce testing costs in memory circuit manufacturing because it makes it possible to shorten the time required.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the basic configuration and basic principle of the present invention, and FIG. 2 is a diagram showing signals of each circuit section for explaining the operation of FIG. 1. Further, FIG. 3 is a diagram showing a specific embodiment of the present invention. In the figure, 1... self-oscillation circuit, 2...
...Binary counter circuit, 3...Description 1.
Support circuit, 4... Normal/incorrect operation determination circuit, 5, 8...
...Input terminal, 6...Output terminal, 7...
...Data input signal terminal, 301...Input terminal, 3
02... Output of G2, 303... G4
Output, 304...First oscillation output, 306...
- Normal/incorrect operation determination terminal, 307... Input terminal. \~, -17)

Claims (3)

[Claims] (1) A semiconductor memory circuit device comprising a self-oscillation circuit and a counter circuit for counting oscillation output signals of the self-oscillation circuit on the same chip. (2) The semiconductor memory circuit device according to claim (1), wherein the output of the counter circuit is used as an address signal for a memory circuit section in the same chip as the counter circuit. (3) A circuit for comparing the output of a storage circuit and a data input signal to detect whether or not the storage circuit is operating correctly is included in the same chip.
2) The semiconductor memory circuit device described in item 2).