JPS6031260A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS6031260A
JPS6031260A JP58140842A JP14084283A JPS6031260A JP S6031260 A JPS6031260 A JP S6031260A JP 58140842 A JP58140842 A JP 58140842A JP 14084283 A JP14084283 A JP 14084283A JP S6031260 A JPS6031260 A JP S6031260A
Authority
JP
Japan
Prior art keywords
substrate
thin film
pattern
resist
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58140842A
Other languages
Japanese (ja)
Inventor
Yasushi Suda
康司 須田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58140842A priority Critical patent/JPS6031260A/en
Publication of JPS6031260A publication Critical patent/JPS6031260A/en
Pending legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PURPOSE:To prevent the discoloration of a substrate by complete removal of resist residue by a method wherein pure water jet washing and solvent vapor phase drying are carried out before high temperature heat treatment in the air after the photo resist on the substrate surface is exfoliated. CONSTITUTION:A Ta thin film 2 and a well-conductive metal 3 are adhered on the surface of the ceramic substrate 1, and then selectively removed by etching, resulting in the formation of a thin film circuit pattern. An NiCr-Pd-Au metallic film 6 is deposited on the back surface of this substrate 1, the photo resist 7 for pattern protection being provided on the substrate surface, and the photo resist 8 for pattern formation on the substrate back, respectively, and then the metallic film 6 is selectively etched. After exfoliation of the photo resists 7 and 8, foreign matters and resist residue are removed by a pure water jet washing 9 under a jet pressure of approx. 80-100kg/cm<2>, and the solvent drying and washing is performed, and the substrate is heat-treated in the ambient air.

Description

【発明の詳細な説明】 ♀発明は混成集積回路の製造方法に係り、特に1g頼件
の優れた高品質なタンタル薄膜回路の製造方法に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a hybrid integrated circuit, and particularly to a method for manufacturing a high quality tantalum thin film circuit with an excellent 1g requirement.

従来、同一基板の両面へ、異なった金九膜を形成する薄
膜回路の製造方法は、大路次のとおりである。先ず、ガ
ラス又はセラミyり等の絶縁基板上にタンタル系薄膜を
スパッタリング法で被着し、更に該膜上にNiCr−P
d−Au又は’l’i −Pd −Au等の良導電性金
属膜をスパッタリング法又は真空蒸着法で形成する。次
に、公知のフォトレジスト処理で前記金属膜を段階的に
選択エツチングし、所望とする薄膜パターンを形成する
。次に、前記基板の裏面にN iCr−AuまたはNi
Cr −Pd −Au寺の金属膜をスパッタリング法で
付着ぜしめ、核金楓膜を同様にフォトレジスト処理で所
望のY!、 L%パターンを形成する。
Conventionally, a method for manufacturing a thin film circuit in which different gold films are formed on both sides of the same substrate is as follows. First, a tantalum-based thin film is deposited on an insulating substrate such as glass or ceramic by sputtering, and then NiCr-P is deposited on the film.
A highly conductive metal film such as d-Au or 'l'i-Pd-Au is formed by sputtering or vacuum evaporation. Next, the metal film is selectively etched step by step using a known photoresist process to form a desired thin film pattern. Next, NiCr-Au or Ni is deposited on the back side of the substrate.
A metal film of Cr-Pd-Au is deposited by sputtering, and the nuclear maple film is similarly treated with photoresist to form the desired Y! , forming an L% pattern.

しかしながら、上記製造方法によれC,1%基机裏面へ
の薄膜パターン形成の際、表面に形成さ牡ているパター
ンのエツチング処理での損傷を防ぐために、当然パター
ン面を促成するための、フォトレジストをコーティング
する。この際、該フォトレジストはパターン部のみなら
ず基板表面も被っCいる。基板材質がセラミック等を用
いCいる場合、該基板表面上の7オトレジストの剥離処
理での除去性は、金属膜上と異なり比較的不安定であり
、淘<フォトレジスト残渣が残る危険性が多分にある。
However, when forming a thin film pattern on the back surface of the C.1% substrate using the above manufacturing method, in order to prevent the pattern formed on the surface from being damaged during the etching process, a photo film is naturally used to promote the pattern surface. Coat the resist. At this time, the photoresist covers not only the pattern portion but also the surface of the substrate. When the substrate material is ceramic or the like, the removability of the photoresist on the surface of the substrate during peeling is relatively unstable, unlike on a metal film, and there is a high risk that photoresist residue will remain. It is in.

この状態で高温熱処理を行うと、前記フォトレジスト残
渣と基板とに熱反応が生じ、基イシ表面が薄茶色に変色
し、フォトエツチング処理で形成された薄膜回路の外観
上美観をそこなう。
If high-temperature heat treatment is performed in this state, a thermal reaction will occur between the photoresist residue and the substrate, and the surface of the substrate will turn light brown, detracting from the aesthetic appearance of the thin film circuit formed by photoetching.

本発明の目的は、上記製造方法の欠点を取除いた混成集
積回路の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit that eliminates the drawbacks of the above-mentioned manufacturing methods.

本発明方法は、基板両面に公知のフォトエツチング処理
で薄膜回路パターンを形成し、表面に保獲コーティング
したフォトレジスト及び裏面パターン上のフォトレジス
トを剥離し、大気中で高温熱処理を行うsiJに、噴出
圧80−100 kg/cm2の純水ジェットa浄を施
し、溶剤気相乾燥と孕行うことを特徴とじている、 つぎに実施例により本発明を説明する。
The method of the present invention involves forming a thin film circuit pattern on both sides of a substrate by a known photoetching process, peeling off the photoresist coated on the front surface and the photoresist on the pattern on the back surface, and performing high-temperature heat treatment in the atmosphere. The present invention is characterized by applying pure water jet a purification at a jetting pressure of 80 to 100 kg/cm2, followed by solvent vapor phase drying. Next, the present invention will be explained with reference to Examples.

第1図から第7図は、本発明によるタンタル薄膜抵抗の
製造工程ヶ7ハす断面図である。まず、第1図に示すよ
うに、充分に洗η号したセラミック基板IKスパッタリ
ング法によりタンタル系薄膜2を約600A被着し、つ
いで同方法でNiCr7000A 、 Au 3000
A、更に無電解メッキ法でAuを約3〜4μm程度付着
させた良導電性金属膜3を形成する。つぎにネガ型フォ
トレジスト4を約3μmの厚さで塗布する。次に第2図
のように、公知の7オトレジスト処理で選択的に良導電
性金属膜3をエツチングし、所望の導体パターンを形成
する。
1 to 7 are cross-sectional views showing seven steps in the manufacturing process of a tantalum thin film resistor according to the present invention. First, as shown in FIG. 1, a tantalum-based thin film 2 of about 600A was deposited on a thoroughly cleaned ceramic substrate using the IK sputtering method, and then NiCr7000A and Au3000 were deposited using the same method.
A. Further, a highly conductive metal film 3 is formed by adhering Au to a thickness of about 3 to 4 μm using an electroless plating method. Next, a negative photoresist 4 is applied to a thickness of about 3 μm. Next, as shown in FIG. 2, the highly conductive metal film 3 is selectively etched using a well-known 7-etch resist process to form a desired conductor pattern.

次に第3図のように、前記基板上に再度ポジ型フォトレ
ジスト5を約3μmの厚さで均一に塗布し。
Next, as shown in FIG. 3, a positive photoresist 5 is uniformly coated on the substrate again to a thickness of about 3 μm.

公知のプリベーク、露光、現像、ポストベークを施し、
所望のフォトレジストハターンを形成する。
Perform known pre-baking, exposure, development, and post-baking,
Form the desired photoresist pattern.

次に第4図のように、前記基板をフッ酸、硝酸。Next, as shown in FIG. 4, the substrate is treated with hydrofluoric acid and nitric acid.

酢酸の混合液からなるエツチング液で鮪出タンタル薄膜
2を除去した後、パターン上のフd、 )レジストは剥
離液を用い除去する。
After removing the tantalum tantalum thin film 2 with an etching solution consisting of an acetic acid mixture, the resist on the pattern is removed using a stripping solution.

次に第5図のように、前記基Aνの裏面にスバ。Next, as shown in FIG. 5, a strip is formed on the back surface of the group Aν.

クリング法又は真空蒸着法でN + Cr J’ d 
A ++ 構成膜6を約400OA付着せしめる。
N + Cr J' d by Kling method or vacuum evaporation method
Approximately 400 OA of A ++ component film 6 is deposited.

次に第6図のように、該基板の表…1にエツチ7グ保睡
用としてネガ型7.トレジスト層7を約5μmの厚さで
形成し、十分乾燥を施した後、該基板裏面の金属膜6の
上にネガ型フォトレジスト8を約4μm塗布し、公知の
7メトレジスト処理で選択エツチングし、所望のパター
ンを形成する。
Next, as shown in FIG. 6, a negative type 7. After forming a photoresist layer 7 with a thickness of about 5 μm and sufficiently drying, a negative photoresist 8 of about 4 μm is coated on the metal film 6 on the back side of the substrate, and selectively etched using a known 7-metresist process. , form the desired pattern.

次に第7図のように、前記基板上のフォトレジスト7お
よび8を公知の剥^IF方法で除去した後、基板表面上
に噴出圧80〜1 (l Okg/cm2の純水ジェッ
ト洗が9をM11シ、異物やレジスト残渣を除去した稜
、溶剤乾燥洗浄し、両面にDf望の〜膜パターンを形成
する。仄に前記基板を・290℃7時間の安定化のため
の大気中熱処理をし、薄膜回路を製造する。
Next, as shown in FIG. 7, after removing the photoresists 7 and 8 on the substrate by a known stripping IF method, pure water jet cleaning at a jet pressure of 80 to 1 kg/cm2 is applied to the substrate surface. 9 to M11, remove foreign matter and resist residue, dry and clean the edges with a solvent, and form the desired Df film pattern on both sides.Then, the substrate is heat treated in the air at 290°C for 7 hours for stabilization. and manufacture thin film circuits.

以上の如く、両面に異なった金属膜構成のパターンを有
した薄膜抵抗基板を製造する上で、裏面#膜パターンを
形成する際、表面パターンを保護するフォトレジストが
数回の熱処理でセラミック表面との密着が増し、ウェッ
ト方式の剥峻では十分に除去できない危険性が多々生じ
たが、本発明の如く、高圧純水ジェット洗浄でセラミッ
ク表面上の7オトレジスト残渣は除去され、高温熱処理
でのセラミック表面の変色は皆無となり、外観をそこな
わない高品質の混成集積回路の製造方法が可能となる。
As described above, when manufacturing a thin film resistor substrate with patterns of different metal film compositions on both sides, when forming the #film pattern on the back side, the photoresist that protects the front pattern is heated several times to bond to the ceramic surface. However, as in the present invention, the 7 otoresist residue on the ceramic surface was removed by high-pressure pure water jet cleaning, and the ceramic was removed by high-temperature heat treatment. There is no discoloration of the surface, making it possible to manufacture high-quality hybrid integrated circuits without damaging the appearance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図から第7図は本発明の一実施例を説明する為の混
成集積回路の製造工程110の断面図である。 l・・・・・・セラミック基板、2・・・・・・タンタ
ル系薄膜、3−− N ic r −Au−Auメ、キ
構成膜、4 、8−・・・°°ネガ型フォトレジスト、
5・・・・・・ポジ型)、トレジスト、6・・・・・・
NiCr−Pd−Au構成膜、7・・印・エツチング保
護膜(ネガ型)4−1・レジスト)、9・・・・・・純
水ジェット。 代理人 弁理士 内 原 日1..:
1 to 7 are cross-sectional views of a hybrid integrated circuit manufacturing process 110 for explaining one embodiment of the present invention. 1...Ceramic substrate, 2...Tantalum thin film, 3--Nicr-Au-Au film, main constituent film, 4, 8-...°°Negative photoresist ,
5...Positive type), Tresist, 6...
NiCr-Pd-Au composition film, 7... mark, etching protective film (negative type) 4-1, resist), 9... pure water jet. Agent Patent Attorney Hi Hara Uchi 1. .. :

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上にタンタル系薄膜抵抗を形成し、この薄膜抵
抗部分1:#c+前記絶縁基板上に形成したエンチング
保静膜を除去し、さらに前記タンタル薄膜抵抗安定化の
だめの大気中での高温熱処理することを含む混成集積回
路の製造方法において、前記熱処理を行う前に前記絶縁
基板に対し、ジヱ7ト洗浄を施すことを特徴とする混成
集積回路の製造方法。
A tantalum-based thin film resistor is formed on an insulating substrate, this thin film resistor portion 1:#c+ the etching retention film formed on the insulating substrate is removed, and further high temperature heat treatment is performed in the atmosphere to stabilize the tantalum thin film resistance. 1. A method of manufacturing a hybrid integrated circuit comprising: performing a heat treatment on the insulating substrate before performing the heat treatment.
JP58140842A 1983-08-01 1983-08-01 Manufacture of hybrid integrated circuit Pending JPS6031260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58140842A JPS6031260A (en) 1983-08-01 1983-08-01 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58140842A JPS6031260A (en) 1983-08-01 1983-08-01 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6031260A true JPS6031260A (en) 1985-02-18

Family

ID=15277979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58140842A Pending JPS6031260A (en) 1983-08-01 1983-08-01 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6031260A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6092537A (en) * 1995-01-19 2000-07-25 Mitsubishi Denki Kabushiki Kaisha Post-treatment method for dry etching
CN102280372A (en) * 2011-09-05 2011-12-14 上海集成电路研发中心有限公司 Method for cleaning semiconductor silicon wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6092537A (en) * 1995-01-19 2000-07-25 Mitsubishi Denki Kabushiki Kaisha Post-treatment method for dry etching
CN102280372A (en) * 2011-09-05 2011-12-14 上海集成电路研发中心有限公司 Method for cleaning semiconductor silicon wafer

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