JPS6029805A - Programmable controller - Google Patents

Abstract

PURPOSE:To perform high-speed processing by generating a couple of special timing pulses which have a mutual phase difference of one cycle, and using them as the arithmetic condition of a sequence program. CONSTITUTION:This controller has a microprocessor and image memories for processor input and output. This arithmetic processing uses a special timing pulse 13 which turns on for one of, for example, every three cycles and a special timing pulses 14 which has a phase delay of two cycle together with step numbers 1 of the program. Consequently, a program instruction which is outputted to an A/D converter to specify a read-in channel is executed in this ON cycle while an input XOO and the special timing pulse 13 for a data readout command, or the special pulse for a storage command B to a register and a specification reset command C for a read-in channel is regarded as processing start condition.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable controller (hereinafter abbreviated as PC) used as an automatic control device with each Yuzu automation machine.

Conventionally, there has been a PC of this type as shown in FIG.

In the figure, (1) is a microprocessor unit (hereinafter abbreviated as CPU unit), and this CPU unit (1) includes a CPU main body (2), a ROM for controlling the CPH (
81. RAM for CPU control (4), RA for temporary storage of sequence programs, timers, counters, etc.
M (5J, comprising a sequence program memory (6), a process input image memory (7), and a process output image memory (8), and (9) is connected to the CPU unit (1). The process input image memory (A) or the process output image memory (81K) is an input/output unit that is accessed from the 81K.

Next, the concept of the arithmetic processing of the conventional PCK sequence program having the above configuration will be explained with reference to FIG.

In FIG. 2, the sequence program αol of the PC indicated by n has a program step number Cu1l from 0 to n.
The program consists of (n+1) steps up to and including step 0, starts from step 0, and ends with one instruction (8) of step n. After that, executes END processing regarding the microcomputer system and proceeds to step 0 processing. It's starting to go back.

In this way, the time from starting the processing of step 0 to executing the processing up to step n until returning to step 0 again is generally referred to as one scan time.

FIG. 3 shows an example in which a conventional sequence program includes a sequence circuit shown in the one-way ladder system of FIG. In Fig. 3, step 1 with step number αη shows the sequence processing of the part corresponding to the circuit of Fig. 4, and this sequence processing reads the current value or voltage value as an analog quantity and converts 7n into a digital quantity. This is an example of a case where a so-called analog-to-digital converter (abbreviated as an A/D converter), which converts the data and supplies it as sequence program arithmetic processing data to a PC unit, is used for the input/output crab unit. The processing outline of that part of the sequence program is as follows.

L, D X0O-... A/D converter data reading salt 9 command.

SET Y n 0 11-- Output to A/D & converter and specify read channel constant (n is 1, 2, 3...).

MOV K3Xn [I DO---A/D Input signal from K converter (XnO, Xnl 11@11 Xn
9. XnA.

Data record of XnB's 12th Register DO number [16 bit 2 data register].

R8T YnO --- Output to A/D converter and read channel (cancellation of seasonal designation.

The above program instructions read the data of the specified channel of the A/D converter and store the contents in the specified data register. Also, of course,
There is a case where data of multiple channels (n=1.2.3m) are read in sequence, and in that case, it can be realized by processing a program similar to the above.

Generally, it is well known that the unit processing time of a PC (for example, per step) is longer for accessing the input/output unit than for accessing memory.Therefore,
In a sequence program such as the above example, in which accesses to input and output crab units are inverted, one scan time becomes long, and a timer that requires fast processing is used.
Counter accuracy deteriorates.

Therefore, in order to solve this inconvenience, the inventors decided to access the input/output crab bits that occur in the process from step 0 to n (END) of the sequence program once in the memory (instead of accessing them each time). A method (referred to as the image memory refresh method) is adopted in which the contents of the buffer memory are actually accessed to the input/output crab unit at the time of END processing after input/output image processing is performed in the buffer memory (buffer memory for access signals to the input/output crab unit) 173. Ta. This greatly improves the reduction in one scan time of the scene program.

However, if such an image memory refresh method is adopted, the output Y in FIGS.
nOu, image processing in memory is as per the program,
BET YnO-+ MOV K3Xn(l DO-+
When running with R8TYnO, access to the actual output unit in the END process is scan RAT.
Only YnO is enabled, i.e. YnO=0(OF
A disadvantage arises in that the state of F) is the output signal fL, and the input signal from the A/D converter is not captured at t'L, which results in rlc.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above.
A programmable controller that can process sequence programs with one scan time shortened by generating a set of special timing pulses with a one-cycle phase difference in a microprocessor and using them as the sequence program calculation conditions. The purpose is to provide four-ra.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 5, α1 is the step number of the program, 0
8) is a special timing pulse F126 that is ONj for only one cycle every three cycles, which is a feature of the present invention. The 0 phrase is a special timing pulse F127 that is delayed by two cycles in phase from the special timing pulse F126 (1B) and turns ON for only one cycle. (b) shows the data acquisition processing cycle of the conventional A/D converter when using the special timing pulse F1260B) and F12704 (
(Nth cycle). Moreover, FIG. 6 shows a sequence circuit of the present invention using special pulses F126 and F127, in contrast to the conventional sequence circuit shown in FIG. 4 that uses a -fC and VD converter.

Program command SET TnO, MOW in Figure 6
K5XnODo, R8T YnOtri Figures 3 to 5
This shows that the process is exactly the same as that shown in part n of the figure.

In FIGS. 5 and 6, program command SET YnO is a data reading command, and input X00 and special timing pulse F126 are processing start conditions.

In addition, the storage command MOV K5YnODo to the register,
Read channel (n) designation cancellation command R8T Yn
In D, read channel designation YnO and special timing pulse F127 are processing start conditions. Therefore, the read channel designation 5FiT YnO performs image processing in the memory in the cycle when the data read command input X00 is ON and the special timing pulse F126 is ON as shown in Figure 5, and refreshes the image memory at the same time as END. , read channel specification and output unit) (YnO) n1 Next, store command to register MOV K3Xn (]
DO and reading channel (n) designation cancellation command RB
T Yn[] performs image processing in the memory in the cycle of special timing pulse F1277% ON when read channel designation YnO is ON, reads data by refreshing the image memory with END, and further issues read command for n channel. is designed to be released.

As is clear from the above example, the read channel (nl
f) N constant BIT YnO and register storage command M
OyK3YnODO and read channel designation cancellation command ROT YnQ are special timing pulses F12
6 and F127, the timing of processing is controlled by n, so even with the image memory refresh method VC aimed at high-speed processing, access to the input/output crab unit can be performed reliably.

In the above embodiment, an example is shown in which the timing cycle of the special timing node is 6 cycles, but the present invention is not limited to this. In some cases, the same effects as in the above embodiments can be achieved even with 2 cycles or 4 cycles.

As described above, according to the present invention, when processing the same person's output code as a plurality of different channel data, it is possible to start and cancel channel-compatible processing for one scan time every fixed scan cycle. N-rL It is configured to control the phase beauty of one cycle using a special timing pulse of one button, which enables high-speed processing and has the effect of providing an economical programmable controller.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing a conventional programmable controller, Figs. 2 and 6 are conceptual diagrams showing arithmetic processing of a conventional programmable controller, Fig. 4 is a conventional sequence program circuit diagram, and Fig. 5 is a diagram of the present invention. FIG. 2 is a sequence program circuit diagram of a programmable controller using special timing pulses according to an embodiment of the invention. (1): Microprocessor (CPU) 2 nits (2
1: CPU main body (81: ROM for controlling the CPU (4) RAM for controlling the Hcptr (5) Temporary storage for the Nisikens program, timer. RAM for counters, etc. ゛(6) Memory for the Nisikens program (γ): Image memory of process input (8): Image memory of process output (9): Input/output crab knit screaming sequence sequence program (11 Ni step number (auxiliary: KND command 03): Special timing pulse F126a sword 2% special Timing pulse F127 In the figure, the same reference numerals are the same, and ``mayt'' indicates the phase. Agent: Masu Oiwa Figure 1 Figure 2 Figure 4 Figure 6 Iq Figure 5 1 Procedure amendment (Spontaneous) 1. Indication of the case Japanese Patent Application No. 58-134009 2, Name of the invention Programmable Controller 3, To the representative Hitoshi Katayama of the person making the amendment Part 6, Contents of the amendment (1) Specification, page 4, No. 8 Correct the description "channel (n)" in line 16 of the same page and line 14 of page 8 to "r channel (0)". (2) r(n) in line 1 of page 5 of the same book. =1.2.3...)
” will be deleted. (3) “Dekaninit (YnO)” on page 8, line 12 of the same book
Change the entry "Access to" to "Output to Dekaninit (SE
T YnO) J and correction su. (4) The description "n channel" on page 8, line 18 of the same book is corrected to "θ channel." (5) The description "Cancel the command" on page 8, line 20 of the same book is corrected to "Cancel the designation by outputting (R9T YnO) j." (6) Change the description r(n)J in the second line of page 9 of the same book to r(
0) Correct as J. (7) In the drawings, Figures 3, 4, and 6 will be corrected as shown in the attached sheets. 7. 1 copy of catalog drawing of attached documents

Claims (2)

[Claims] (1) It is equipped with a microprocessor, an image memory for process input and an image memory for process output that are accessed by the microprocessor, and a ROM and RAM for controlling the microprocessor, a memory for sequence programs, and a sequence program. The microprocessor writes the output timing to the process output and the input timing from the process input to the 0% standard area of the sequence processing RAM, and executes the sequence processing. Write to the above specific address using the program.
A programmable controller that is characterized by accessing the same content. (2) Patent mA, Paragraph 1, characterized in that the t″LkLk process output power timing written to the specific address of the sequence processing RAM and the input timing from the process input have a difference of vc1 to several scan scan times. programmable controller.