JPS6028688A - Inspector for display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a display control device for checking the normality of the operation of a display control device that generates display signals for displaying characters, figures, etc. and performs display control on a display device. test equipment.

Conventionally, this type of inspection is carried out by connecting the output of a display control device to a text/graphics display and allowing an inspector to visually check the display on the text/graphics display. In the above-mentioned conventional inspection, the inspector always sees the displays that appear one after another on the display device and ]:! There is peace of mind in checking i++,', the burden of inspection is heavy, and even between -11i'i, there is a drawback that if [1 is removed, inspection will be omitted and detailed inspection items will not be checked sufficiently. That is, the quality of the inspection ('5) is poor, and there are many drawbacks such as the long time required for inspection.

An object of the present invention is to overcome the above-mentioned conventional drawbacks and to provide an inspection device for a display control device, which can automatically check the normality of a display control device accurately and quickly. There is a particular thing.

The testing device of the present invention is a testing device for a display control device that tests the normality of the operation of a display control device that supplies display signals for displaying characters, figures, etc. to the display device. A first storage means for storing display patterns, and correct answer display signals are sequentially read from the first storage means in a predetermined arbitrary pattern in synchronization with a display timing signal output from the display control device. a timing generating means for generating a timing signal; a comparing means for detecting coincidence between a display signal outputted by the display control device and an output signal of the first storage means; The present invention is characterized in that it comprises a second storage means for incrementing by 1 according to a timing signal outputted by the means, and a determination means for determining the validity of the display signal based on the contents of the second storage means.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
It is used by directly connecting to the output of the display control device 100. That is, the present inspection device 120 inputs a display signal 111 including character and graphic information output from the display control device 100, a display start signal 112a including information regarding display timing and display position, a display timing signal 112b, etc., and outputs the display signal. , and outputs a determination result signal 121. Note that the display signal 111 may be a parallel signal of a plurality of pits, and the Fj numbers 112 a and 112 b may be serial bits of one signal.

FIG. 2 is a circuit diagram showing details of the inspection device 120. That is, the shift register 300 constitutes a first storage circuit, and has a positive fv (display pattern) stored in advance, and is sequentially read out by a timing signal 361, which will be described later.
Timing signal 3 output from AND circuit 360 which is opened and closed according to an arbitrary pattern stored in advance in 10.
It is given by the rising edge of 61. Since the display timing signal 112b output from the control device is input to the input of the AND circuit 360, the timing signal 36
1 is output in synchronization with the display timing signal 112b and according to a certain pattern stored in the shift register 310. The AND circuit 340 is opened by the output of the register 330 which reads a logic "1" input signal 413 into the shift register 310 and sets the output 331 to a high level at the fall of the display start signal 112a inputted from the display control device. Then, the display timing signal 112b is applied as a read timing signal 341 via the AND circuit 340, and the pattern contents stored in advance are sequentially output bit by bit, and the pattern signal 311 is input to the AND circuit 360.

In this embodiment, t, the shift register 310 and the AND circuit 3
60 and 1-a predetermined arbitrary] timing signal for sequentially reading out correct answer display signals from the first storage means in each turn in synchronization with the display timing output from the display control device. The timing signal generating means constitutes a register 3
30 is activated by the display start signal 112a, and outputs a constant turn timing signal 361. Shift register 3 by timing signal 361
The comparison means 380 compares the signal 301 read from 00 with the display signal 111 input from the display control circuit. The comparison means 380 outputs the coincidence signal 381 as 1" when the input planes match. The comparison means 380 can be formed by, for example, an exclusive disjunction circuit or the like. !'!: 2 storage means, which stores the coincidence signal 38 output from the comparison means 380.
1 is constituted by a shift register with serial and parallel outputs that reads and shifts each time the timing signal 361 falls. The contents of the shift register 320 are:
The signals are output in parallel and input to a multi-input AND circuit 390. The multi-input AND circuit 390 constitutes (t) determining means that determines the validity of the display signal 111 by setting the determination result signal 121 to "1" when the total human power is "1". ing.

In particular, the display to be inspected is a dot pattern in row 1 and column m, as shown in Fig. 3, and the display in the third column is d13°d2. ! +d
s d43+...d, 3 is bright display, other is dark display 2
Assume that it is displayed by a transmission signal. As shown in FIG. 4(a), the display signal 111 output by the display control device is "1" at the positions d131, d231, etc., and is 0" at the other positions. However, at the end of the first row, Display d8.
It is assumed that the display/f bar of the next line is output after an interval of two clocks (1)lI+t)+2.

That is, the display month 111 starts to be transmitted from the falling point of the display start signal 112a as shown in FIG.
It is output in synchronization with h. Note that the interval bn l
During row switching periods such as b12, the display signal 111 is undefined.

When the display start signal 112a rises, the output 331 of the register 330 becomes high level as shown in FIG.
No. 341 is as shown in <I (e). A predetermined pattern is stored in the register 310, and its output No. 14 becomes a pattern as shown in FIG.
This pattern is such that it becomes "0" during the 11th row -v change period. Therefore, an and -circuit 3 (the timing signal 361 for 50 output is the same as shown in the figure (G), the same gate to the display timing signal 112B, and the pattern that is not output is not output. The shift register 30
The positive (indication/%) bit stored in advance as 0 is successively outputted one bit at a time, and as shown in the figure (l).
-8 No. 301 is output. Said spoon 301 and the above indication (
If the revision number 111 matches, display 1 > jllll
is normal, and the matching ft,r output from the comparing means 380
No. 381 becomes "1" ((i) in the same figure). Shift register 3204: i: Shifts the coincidence signal 381 output from the comparing means 380 at each falling edge of the timing signal 361.The display signal 111 is unstable during the row switching period. From this, the ratio bite means 38 during this period
The match signal 381 output by 0 is undefined, but around here.
In between, timing signal 3 is applied to shift register 320.
61 is not supplied, the above undefined output is stored in the shift register 320! do not. Also, Imo indication signal 1
11 is normal, the entire contents of the shift register 320 are
11, and the determination result signal 121 output from the multi-input AND circuit 390 in FIG. 2 is 1'', and the normality of the operation of the display control device is determined.

In the embodiment described above, the display control device fif100 sends the display signal 111 and the signals 112a, 112 indicating the display position, etc.
We have explained the case where the display signals such as b, etc. are output separately, but if the display signal itself output from the display device includes position information and display timing signals, an appropriate extraction circuit is provided to separate the display signals and display timing signals. By separating the timing signal, it is possible to test in a similar manner. In addition, if the target is a video signal in which a display signal and the same J4JJ signal for indicating the display position are combined, as seen in television deviations, the same configuration may be implemented by providing an excessive separation circuit. is possible. Furthermore, in the case where the display signal is composed of a plurality of signals such as a color signal, the logical result of the determination result signals determined for each color may be calculated. In addition, the timing generation means can also be constructed using a delay circuit using resistor content, a counter, etc. without using a shift register, etc. However, it is still possible to generate an arbitrary waveform using a programmable 6-function generator, etc. You can also set it as follows.

Furthermore, it is also possible that the first and second storage means are not shift registers, but arbitrary access storage devices having suitable selection and logic circuits.

As described above, the present invention has 1. - Then, if iFmi, a 10th 1λχ means for storing the output data is used, and a comparison is made to confirm that the output of the first storage means matches the display signal output from the iFmi controller. a second storage means for sequentially storing the output of the output means; and 7. a display output by the display control device in a predetermined pattern in the first and second storage means The timing generation circuit that supplies the timing 1.1 obtained by the same method as the timing generator (Ii't) and the output of the timing generation circuit 2) generates a timing signal l':j+14jL・1'X1. From this, it is possible to quickly and reliably detect the 4CX error of the display signal output from the file display control device, thereby improving the inspection quality. This has the effect of shortening the inspection time.

[Brief explanation of the drawing]

13'S 1 is a block diagram showing an embodiment of the present invention,
FIG. 2 (d) is a block diagram showing the 6=do rule of the inspection device of the above embodiment, FIG. 3 is a diagram showing an example of the display of the target display device 42, and FIG. 4 is a block diagram showing the implementation shown in FIG. 2. This is an evening/time chart without showing the signals of each part in the example.In the figure, 100...display 1hljl+iil device, 111...display signal, 112a...display start signal - bow, 112b...display timing... No. 4, 120・
. . .Result transmission of ``Results'', q, i21...1'll >, 300. 310. 320...Shift V
Register, 301... Shinzuki, 31J... Pattern 1 page number, 330... Register, 331... Output, 34
0. 360... 171 circuit, 341... Read timing signal -r, 301... Timing 11: J4 bar 380... Comparison means, 38■... Match 1. donkey 39
0...Multi-input AND circuit. Agent J1 Kunshi Resident Bj Toshimune Figure 1 12b. ;3rd dn game

Claims (1)

[Claims] In an inspection device for a display control device that inspects the normality of the operation of a display control device that supplies display signals for displaying characters, figures, etc. to a display device, there is a method for storing correct display patterns corresponding to each display position in advance. a first storage means, and a timing guide for reading out the lllLjth correct answer display information from the first storage means in a predetermined arbitrary pattern in synchronization with a display timing signal output from the display control device. a timing generating means for generating a signal; a comparing means for detecting coincidence between a display signal outputted by the display control device and an output signal of the first storage means; ♀ (with a second storage means,
1. An inspection device for a display control device, comprising: determining means for determining the validity of the display signal based on the same number of the second memory hand.