JPS6028399B2 - charge transfer device - Google Patents

charge transfer device

Info

Publication number
JPS6028399B2
JPS6028399B2 JP52160299A JP16029977A JPS6028399B2 JP S6028399 B2 JPS6028399 B2 JP S6028399B2 JP 52160299 A JP52160299 A JP 52160299A JP 16029977 A JP16029977 A JP 16029977A JP S6028399 B2 JPS6028399 B2 JP S6028399B2
Authority
JP
Japan
Prior art keywords
charge transfer
transfer device
growth layer
thickness
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52160299A
Other languages
Japanese (ja)
Other versions
JPS5492186A (en
Inventor
良育 東迎
伸夫 佐々木
良彦 比嘉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52160299A priority Critical patent/JPS6028399B2/en
Publication of JPS5492186A publication Critical patent/JPS5492186A/en
Publication of JPS6028399B2 publication Critical patent/JPS6028399B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/762Charge transfer devices
    • H01L29/765Charge-coupled devices
    • H01L29/768Charge-coupled devices with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 本発明は、電荷転送に方向性を有するSOS−MOS構
造の電荷転送装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer device having an SOS-MOS structure that has directionality in charge transfer.

電荷転送装置は、MOS構造の電極に電圧をかけること
によってシリコン基板の表面に空乏層の領域をつくって
少数電荷を蓄積し、荷電電極を移動することによって、
空乏層領域をシリコン基板の表面に沿って移動させ、蓄
積された電荷を順次転送するものある。電荷転送装置に
おいて荷電電極を移動させるための手段として、3相ク
ロックを用いる方法と2相クロックを用いる方法とが行
われている。
A charge transfer device creates a depletion layer region on the surface of a silicon substrate by applying a voltage to an electrode of a MOS structure, accumulates minority charges, and moves the charged electrode.
Some methods move the depletion layer region along the surface of the silicon substrate and sequentially transfer accumulated charges. As a means for moving a charging electrode in a charge transfer device, a method using a three-phase clock and a method using a two-phase clock are used.

2相クロツクを用いる方法は、励振が容易であり小型仲
こ適しているが、反面、電荷の逆流を防止するために特
別の工夫を必要とする。
The method using a two-phase clock is easy to excite and is suitable for small-sized devices, but on the other hand, special measures are required to prevent reverse flow of charges.

電荷転送装置において電極にある電圧を与えたときシリ
コン基板表面領域に生じるポテンシャルの深さは、しき
し、値電圧V仇と逆の大小関係にあり、しきい値電圧V
thは通常次の関係に従うことが知られている。
In a charge transfer device, when a certain voltage is applied to the electrodes, the depth of the potential generated in the surface area of the silicon substrate is inversely related to the threshold voltage V.
It is known that th usually follows the following relationship.

VthニF(NB.tox)ニVG一■′S 、【1’
ここでFはシリコン基板の不純物濃度NB、および基板
表面に形成された酸化物の厚さめxの関数を表わし、又
VGは上記電極に印加する電圧、■′sは上記ポテンシ
ャルの深さを示す量である。
Vth NiF (NB.tox) NiVG1■'S, [1'
Here, F represents a function of the impurity concentration NB of the silicon substrate and the thickness x of the oxide formed on the substrate surface, VG represents the voltage applied to the above electrode, and ■'s represents the depth of the above potential. It's the amount.

電荷の転送はポテンシャルの深い方向に行われるので、
従って電荷転送に方向性を与え、電荷の逆流を防止する
ためには、何らかの手段によってしきし、値電圧Vth
に変化を与え、構造上の非対称性を生ぜしめればよい。
第1図および第2図はこのようにして作られた、従釆の
電荷転送装置の例を示したものである。
Since charge transfer occurs in the deep direction of the potential,
Therefore, in order to give directionality to charge transfer and prevent charge backflow, it is necessary to use some means to threshold the value voltage Vth.
All you have to do is change the structure and create a structural asymmetry.
FIGS. 1 and 2 show an example of a secondary charge transfer device made in this manner.

第1図の例においては、シリコン基板1の上に形成され
た酸化膜2は、各素子ごとにその厚さbxを一部におい
て異ならしめてあり、また第2図の例においては電極3
の下にあるシリコン基板1の部分の一部に不純物濃度N
Bの大きい部分4が設けてある。
In the example of FIG. 1, the thickness bx of the oxide film 2 formed on the silicon substrate 1 is partially different for each element, and in the example of FIG.
There is an impurity concentration N in a part of the silicon substrate 1 under
A large portion 4 of B is provided.

従って‘1}式の関係から第1図の例においては酸化膜
の厚さの大きい部分に、第2図の例においては不純物濃
度の大きい部分に、電極の下のシリコン基板にしきし、
値電圧の大きい部分を生じ、これによるポテンシャルレ
ベルの非対称性によって、端子■,,■2に2相クロッ
クを与えたときの電荷の移動に方向性を生じる。
Therefore, from the relationship of equation '1}, in the example of FIG. 1, the oxide film is applied to the thick part, in the example of FIG. 2, the impurity concentration is large, and to the silicon substrate under the electrode.
A portion with a large value voltage is generated, and the resulting asymmetry of the potential level causes directionality in the movement of charge when a two-phase clock is applied to terminals (2), (2), and (2).

しかしながら、酸化膜の厚さを部分的に変えたり、シリ
コン基板の一部の不純物濃度を変えたりすることは、前
者の場合は工程の複雑化や技術的困難を伴いまた後者の
場合はマスクを何種類も必要とする結果製造工程が甚だ
複雑となり、いずれにしても価格の上昇を招きやすい欠
点があった。
However, partially changing the thickness of the oxide film or changing the impurity concentration of a part of the silicon substrate requires complicated processes and technical difficulties in the former case, and requires a mask in the latter case. As a result of requiring multiple types, the manufacturing process becomes extremely complicated, and in any case, there is a drawback that this tends to lead to an increase in price.

本発明の目的は、このような従来技術の欠点を解消した
電荷転送装置を提供することにあり、その手段としてS
OS−MOS構造の電荷転送装置においてシリコンェピ
タキシャル成長層の厚さを選択的に変えることによって
しきい値電圧を制御し電荷転送に方向性を与えたことを
特徴とするものである。SOS一MOS構造は、サフア
イャやスピネル等の絶縁基板上にシリコンをェピタキシ
ャル成長させた層を形成し、このシリコンェピタキシヤ
ル成長層の表面を酸化させて酸化膜を作ったものである
An object of the present invention is to provide a charge transfer device that eliminates the drawbacks of the prior art, and as a means thereof, S
A charge transfer device having an OS-MOS structure is characterized in that the threshold voltage is controlled by selectively changing the thickness of the silicon epitaxial growth layer to give directionality to charge transfer. In the SOS-MOS structure, a layer of silicon is epitaxially grown on an insulating substrate such as saphire or spinel, and the surface of this silicon epitaxially grown layer is oxidized to form an oxide film.

このようなSOS−MOS構造におけるシリコンェピタ
キシャル成長層の部分のしきい値電圧ythは、その厚
さtが減少するとともに次第に増加する。
The threshold voltage yth of the silicon epitaxially grown layer in such an SOS-MOS structure gradually increases as its thickness t decreases.

第3図はこのようなしきい値電圧Vthと厚さtとの関
係を示すデータの一例である。これはェピタキシャル成
長によって形成されたシリコン単結晶層の格子欠陥が界
面付近で最も多く、厚さが増すにつれて次第に減少する
ことに基づいているものと考えられる。本発明は、この
現象を利用してシリコンヱピタキシャル成長層のしきい
値電圧を制御することによって電荷転送に方向性を生ぜ
しめるものである。
FIG. 3 is an example of data showing the relationship between such threshold voltage Vth and thickness t. This is considered to be based on the fact that lattice defects in a silicon single crystal layer formed by epitaxial growth are most numerous near the interface and gradually decrease as the thickness increases. The present invention utilizes this phenomenon to control the threshold voltage of the silicon epitaxial growth layer, thereby creating directionality in charge transfer.

以下、実施例について本発明を詳細に説明する。Hereinafter, the present invention will be described in detail with reference to Examples.

第4図aは本発明の電荷転送装置の一実施例の構成を示
す断面図である。
FIG. 4a is a sectional view showing the structure of an embodiment of the charge transfer device of the present invention.

第4図aにおいて11はサフアィャ等からなる基板であ
り、その上にシリコンェピタキシャル成長層12を有す
る成長層12の表面は一様に酸化されて酸化膜13を形
成しており、さらにその上にアルミニウム等の金属から
なる電極14−,,14‐2,14‐3,14‐4,…
…が付されている。成長層12の厚さは部分的に異なら
しめてあり、薄い部分12−,,と厚い部分12‐2,
とはそれぞれ厚さら,t2を有し、かつ、薄い部分と厚
い部分は交互に配列され、さらにこれらの1組ごとに電
極が設けられて、順次同一方向に繰り返し配置されてい
る。
In FIG. 4a, reference numeral 11 denotes a substrate made of Safya or the like, on which a silicon epitaxial growth layer 12 is formed.The surface of the growth layer 12 is uniformly oxidized to form an oxide film 13, and further on Electrodes 14-,, 14-2, 14-3, 14-4,... made of metal such as aluminum
... is attached. The thickness of the growth layer 12 is partially different, with a thin part 12-,, and a thick part 12-2,
have a thickness of t2, and the thin portions and thick portions are arranged alternately, and electrodes are provided for each set of these and are repeatedly arranged in the same direction.

今、1つおきの電極14−,,14‐3,・…・・に接
続された端子■,と、電極14‐2,14‐4,・・・
・・・に接続された端子■2とをそれぞれ一括して2相
クロツクを印加する。
Now, the terminal ■, connected to every other electrode 14-,, 14-3, . . . and the electrodes 14-2, 14-4, .
A two-phase clock is applied to each of the terminals connected to terminals 2 and 2 at once.

端子■,にクロツク電圧が与えられ、端子■2には与え
られないときは、シリコン基板におけるポテンシャルは
、端子■,に接続された電極の下の薄い成長層の部分1
2−,と厚い成長層の部分12‐2とでは異なっている
。しかしてこの関係は第3図に示された厚さちおよびり
こ対するしきい値電圧Vth,およびVtムの関係に‐
対応している。従って、電極14−,,14‐3,・・
・・・・の下の成長層に生じるポテンシャルは、第4図
bに示されたごと〈段階的に生じて、厚い成長層の部分
12‐2において深く、この部分の空乏層に少数荷電が
蓄積する。次に、端子■2にクロツク電圧が与えられ、
端子○,には与えられないときには同様にして第4」図
dのごとく同様なポテンシャルを端子■2に接続された
電極の下の成長層に生じるが、過渡期においては第4図
cに示すごとく段階的に異なる分布を生じる。
When a clock voltage is applied to terminal 2, but not to terminal 2, the potential in the silicon substrate is equal to the part 1 of the thin growth layer under the electrode connected to terminal 2.
2-, and the thick growth layer portion 12-2. However, this relationship is similar to the relationship between the threshold voltage Vth and Vt for the thickness and thickness shown in FIG.
Compatible. Therefore, electrodes 14-,, 14-3,...
As shown in Fig. 4b, the potential generated in the growth layer below ... occurs in stages, and is deep in the thick growth layer part 12-2, where minority charges are present in the depletion layer. accumulate. Next, a clock voltage is applied to terminal ■2,
When no voltage is applied to terminal ○, a similar potential is generated in the growth layer under the electrode connected to terminal ○2, as shown in Figure 4 (d), but in the transition period, as shown in Figure 4 (c). This gives rise to different distributions in stages.

従って端子■,に接続された電極の下の厚い成長層の部
分に蓄積された電荷は容易に端子■2 に接続された電
極の下の厚い成長層の部分に移動する。このようにして
端子■,と■2における2相クロック電圧のオンオフに
伴って電荷は順次右向きに移送され、第4図aに示され
た装置は電荷転送装置として動作する。
Therefore, the charge accumulated in the portion of the thick growth layer under the electrode connected to terminal 2 easily moves to the portion of the thick growth layer under the electrode connected to terminal 2. In this way, charges are sequentially transferred to the right as the two-phase clock voltages at the terminals 1 and 2 are turned on and off, and the device shown in FIG. 4a operates as a charge transfer device.

第4図aに示す電荷転送装置の製作は次のような順序で
行われる。まず、サフアィャ等の基板上に一様の厚さに
シリコンェピタキシャル成長層を形成する。次に厚い成
長層の部分に対応する位置にレジスト層を設けたのちエ
ッチングを行って薄い成長層の部分を薄くする。レジス
ト層を除去したのち酸化して、成長層の表面全体に一様
な厚さの酸化膜を形成する。これにアルミニウム等の金
属を黍着したのち、素子と素子の境界部分を金属膜を切
断して電極を形成する。以上説明したように本発明の電
荷転送装置は、SOS−MOS構造におけるシリコンェ
ピタキシャル成長層のしきし、値電圧が成長層の厚さに
よって異なることを利用して、成長層の厚さを選択的に
制御することによって簡単な構造で電荷転送装置を形成
することができ、その製造工程も簡易であり、従って実
用上におけるその価値は極めて大きいものである。
The charge transfer device shown in FIG. 4a is manufactured in the following order. First, a silicon epitaxial growth layer is formed to a uniform thickness on a substrate such as Safya. Next, a resist layer is provided at a position corresponding to the thick growth layer, and then etching is performed to thin the thin growth layer. After the resist layer is removed, it is oxidized to form an oxide film with a uniform thickness over the entire surface of the grown layer. After coating this with a metal such as aluminum, the metal film is cut at the boundary between the elements to form an electrode. As explained above, the charge transfer device of the present invention selects the thickness of the grown layer by utilizing the fact that the threshold voltage of the silicon epitaxial growth layer in the SOS-MOS structure differs depending on the thickness of the grown layer. By controlling the method, a charge transfer device can be formed with a simple structure, and its manufacturing process is simple, so its practical value is extremely great.

【図面の簡単な説明】 第1図および第2図は従来の電荷転送装置の礎成を示す
図、第3図はシリコンェピタキシャル成長層におけるし
きい値電圧と厚さとの関係を示す図、第4図は本発明の
電荷転送装置の一実施例の構成を示す断面図である。 1:シリコン基板、2:酸化膜、3:電極、4:不純物
濃度の大きい部分、11:サフアィャ等の基板、12:
シリコンヱピタキシャル成長層、12−,:薄い成長層
の部分、12‐2・・・:厚い成長層の部分、13:酸
化膜、14−,,14‐2,14‐3,14‐4,・・
・:電極。 ガー餌 オ2囚 ガ3図 ガ4函
[Brief Description of the Drawings] FIGS. 1 and 2 are diagrams showing the basic structure of a conventional charge transfer device, and FIG. 3 is a diagram showing the relationship between threshold voltage and thickness in a silicon epitaxial growth layer. FIG. 4 is a sectional view showing the structure of an embodiment of the charge transfer device of the present invention. 1: Silicon substrate, 2: Oxide film, 3: Electrode, 4: Portion with high impurity concentration, 11: Substrate such as Safya, 12:
Silicon epitaxial growth layer, 12-,: thin growth layer portion, 12-2...: thick growth layer portion, 13: oxide film, 14-,, 14-2, 14-3, 14-4,・・・
·:electrode. Gar bait, 2 captive moths, 3 figure moths, 4 boxes

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁基板上に形成されたエピタキシヤル層と、該エ
ピタキシヤル層上に形成された一様な膜厚の絶縁膜と、
該絶縁膜上に設けられた複数の電極を有し、 該エピ
タキシヤル層は膜厚の厚い部分と薄い部分とを交互に有
し、該厚い部分上に設けられた電極と薄い部分上に設け
られた電極には異なる位相の信号が与えられるように構
成されてなることを特徴とする電荷転送装置。
1. an epitaxial layer formed on an insulating substrate; an insulating film with a uniform thickness formed on the epitaxial layer;
The epitaxial layer has a plurality of electrodes provided on the insulating film, the epitaxial layer has thick parts and thin parts alternately, and the electrodes are provided on the thick part and the electrodes are provided on the thin part. A charge transfer device characterized in that the charge transfer device is configured such that signals of different phases are applied to the electrodes.
JP52160299A 1977-12-29 1977-12-29 charge transfer device Expired JPS6028399B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52160299A JPS6028399B2 (en) 1977-12-29 1977-12-29 charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52160299A JPS6028399B2 (en) 1977-12-29 1977-12-29 charge transfer device

Publications (2)

Publication Number Publication Date
JPS5492186A JPS5492186A (en) 1979-07-21
JPS6028399B2 true JPS6028399B2 (en) 1985-07-04

Family

ID=15711954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52160299A Expired JPS6028399B2 (en) 1977-12-29 1977-12-29 charge transfer device

Country Status (1)

Country Link
JP (1) JPS6028399B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01164766A (en) * 1987-12-18 1989-06-28 Inax Corp Method for calcining accessary tile
JPH0327280Y2 (en) * 1985-05-30 1991-06-12

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0327280Y2 (en) * 1985-05-30 1991-06-12
JPH01164766A (en) * 1987-12-18 1989-06-28 Inax Corp Method for calcining accessary tile

Also Published As

Publication number Publication date
JPS5492186A (en) 1979-07-21

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