JPS6028244A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten the surface, and to obtain a wiring having no stepped section by a method wherein a buried layer is formed to the surface layer section of a semiconductor substrate, an epitaxial growth layer is formed to the whole surface containing the bureid layer, the growth layer is isolated insularly including the buried layer, the surface of the active region is projected, the surface surrounding the surface of the active region is buried with an oxide isolating film and the wiring is formed on the oxide isolating film. CONSTITUTION:A buried layer 4 is diffused and formed to the surface layer section of an Si substrate 1, a semiconductor layer 2 is grown on the whole surface containing the buried layer in an epitaxial manner, and the layer 2 is formed insularly by a channel stopper 3. A base region 8, an emitter region 9a positioned in the region 8 and a collector 10a projecting from the region 4 are shaped in the layer 2, and the outside of the insular layer 2 and the layer 2 between the regions 8 and 10a are removed through etching. The removed section is buried with an oxide isolating film 5 while flattening the surface, a polycrystalline Si layer 6a for a wiring is applied on the whole surface containing the insular layer 2, metallic silicide layers 11a are formed at predetermined positions, and the surface is coated with an intermediate insulating film 12a and a window 13a is bored and a second layer wiring layer 14a is attached thereon.

Description

[Detailed Description of the Invention] (Technical Field) This invention reduces the chip area of bipolar ICs that apply oxide film separation in semiconductor integrated circuits, and makes it possible to easily obtain multilayer wiring. The present invention relates to a method for manufacturing a semiconductor device.

(Prior art) In many bipolar ICs that apply conventional oxide film separation, the wiring area occupies most of the chip, and the oxide film area must be widened, which is a major obstacle to reducing the chip area. It had become.

Furthermore, since a resistor was also formed in the active region, an IC with a circuit configuration having a large number of resistors required a large area, which was also an obstacle to reducing the chip area.

FIG. 1 shows a cross-sectional view of a bipolar IC with a conventional structure. In FIG. 1, an epitaxial growth layer 2 is formed on a silicon substrate 1, and a channel stop layer 3 is formed on this epitaxial growth layer 2 and the silicon substrate 1.

4 is a buried layer, and 5 is an oxide film isolation region.Most of the wiring is formed on the oxide film isolation region 5. Especially in the case of multilayer wiring, most of the wiring is formed on the oxide film isolation region 5 to reduce the influence of the step difference in the underlying layer. A wiring line is formed on the oxide film isolation region 5.

In particular, in ICs with a logic circuit configuration, the wiring is complicated, so the wiring has a two- to three-layer wiring structure, and the wiring must be made on the patterned film separation region 5, which limits the active area area. It occupies the area on the board.

An epitaxial layer 2 is formed on a silicon substrate 1, a channel stop layer 3 is provided, and a base layer 8, an emitter layer 7, a collector layer 9, and a resistance layer 6 of an active region are formed.

This resistance layer 6 also requires a very large number depending on the circuit configuration, and it was thought that it would be sufficient to place it on the isolation oxide film 5 in order to reduce the chip area, but it is necessary to place it on the wiring area as well. Note that 10 is the first wiring layer, 11 is the intermediate insulating film layer, and 12 is the intermediate insulating film layer.
1 is a second wiring layer, and 13 is a through hole.

(Objective of the Invention) The present invention has been made in order to eliminate these drawbacks, and provides a method for manufacturing a semiconductor device that can provide multilayer wiring with fewer steps and can significantly reduce the chip area. (Structure of the Invention) A method for manufacturing a semiconductor device according to the present invention involves etching a semiconductor substrate onto a platen, leaving a part of the semiconductor substrate including an active region, and etching an oxide layer and a polycrystalline silicon layer. The polycrystalline silicon layer is formed so as to be almost flat with the plateau surface, and impurities are selectively diffused into the polycrystalline silicon layer.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. FIG. 2 is a sectional view showing the structure of a semiconductor device manufactured according to one embodiment, and FIGS. 3(a) to 3Qc) are process explanatory diagrams of this embodiment. This figure 2 and figure 3 (a) - figure 3 (k)
1, the same parts as in FIG. 1 will be described with the same reference numerals.

First, the manufacturing method of the present invention will be outlined with reference to FIG. An epitaxial layer 2 is formed on a silicon substrate 1, a channel stop 3, a buried layer 4 are provided, and an oxide film isolation region 5 is formed.
, after forming the base layer 8, the emitter layer 9a, and the collector layer 10a, the resistance layer 7a is provided, and the metal silicide layer (the wiring polysilicon layer 6a and the metal silicide layer 11a) is used as the wiring, and in the case of multilayer wiring, intermediate insulation film 12a,
After providing the through holes 13, the second layer wiring 14 is formed.

The details of the manufacturing method of the present invention will be specifically explained below with reference to FIGS. 3(a) to 3 (cross-sectional views of shellfish).
As shown in a), after forming a channel stop layer 3 and a buried layer 4 on a silicon substrate 1, an epitaxial layer 2 is grown, and a fluoro-nitric acid etchant is used to grow the epitaxial layer 2, which corresponds to an isolation region, through an oxide film 15 and a nitride film 16. Etch the areas to be removed. For example, if the epitaxial layer 2 is 3μ, it is etched by about 0.7μ.

Next, as shown in FIG. 3(b), an oxide film 5 is formed in a high-pressure oxidation furnace, and the nitride film 16 and oxide film 15 are peeled off. At this time, the height difference in section A is set to be, for example, 0.3 μ.

Next, as shown in FIG. 3(e), an oxide film 22 is formed on the buried layer 4, and a base region 8 is formed by performing known photolithography and diffusion. As shown in FIG.
．． Generates 3μ. Next, a thin oxide film 17 is formed by about 200 people.

Next, as shown in FIG. 3(e), holes are formed in the resist film 18 at the base contact portion 8' and the resistor formation portion 7a by a known photolithography technique, and then the resist film 18 is formed into holes by a known ion implantation technique. Insert an object (in this invention boron).

Next, as shown in FIG. 3(f), the resist film 1 is
9 is implanted into the emitter contact part 9', the collector contact part 10', and the polysilicon layer B part used as wiring using ion implantation technology.
This example is phosphorus).

Next, as shown in FIG. 3(b), oxygen is implanted through the resist film 20 by ion implantation technique in order to convert the unimplanted polysilicon layer B into an insulator.

Next, as shown in FIG. 3(h), by performing cyanyl drive-in using a known diffusion technique, an emitter layer 9a, a collector layer 10a, a resistance layer 7a, and a wiring layer 6a are obtained.

Next, as shown in FIG. 3(i), a resist film 21 is formed on the resistance layer 7a. In this case, make sure that the resistive contact portion C can be removed. Then, a metal layer 11 (platinum in this invention) is deposited.

Next, as shown in FIG. 3(j), the resist film 21 is peeled off using a known lift-off technique, and the remaining metal layer is alloyed. Thereafter, when the metal layer is removed using an etchant (regia regia in this invention), a metal silicide layer 11a remains where only the alloyed portions are silicided. The wiring is now complete.

In this invention, the platinum silicide layer is used as a means to lower the wiring resistance.

Next, in the case of multilayer wiring, as shown in FIG. 3(b), an intermediate insulating film 12a is formed, a through hole 13a is opened, and a second layer wiring 14a is formed.The same procedure is followed. C3
Layer, 4 layers... Perform wiring.

As is clear from the above, the feature of the present invention lies in flattening the isolation region and the active region.
) has been flattened. This is because the isolation region is made 0.3μ lower than the active region at the time of isolation and oxidation, and the polysilicon layer 6a is grown and buried there by 0.3μ.

As a result, the wiring up to the first layer is completely flattened, and a multilayer structure with at least one extra layer than in the prior art is possible.

In addition, by forming the resistance region on the isolated oxidation region, the active area can be reduced, and since the resistance region and the first layer wiring region are also made of polysilicon, they can be formed finely, making it possible to reduce the chip size. became.

In embodiments of the invention, a 50% reduction in logic ICs has been achieved. Furthermore, since the difference in level in the first layer wiring is extremely reduced compared to the conventional method, there is an advantage that no measures against the difference in level, such as a silica film coating, are required.

Although this invention was carried out for bipolar ICs, it can be applied to the manufacture of all ICs, and has the advantage of being particularly capable of flattening and fine wiring.

(Effects of the Invention) As described above, according to the semiconductor device of the present invention, the semiconductor substrate is etched onto the plateau, leaving a portion of the semiconductor substrate including the active region, and the oxide layer and the polycrystalline silicon layer are etched onto the plateau. The polycrystalline silicon layer is formed so that it is almost flat with the surface, and impurities are selectively diffused into the polycrystalline silicon layer, making it possible to form multilayer wiring with few steps and greatly reduce the chip area. Because it is a carrier, even in the photolithography process for two-layer and three-layer wiring, it is possible to turn finer particles than before, which is desirable for higher integration.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an Ibora IC (formed by a conventional semiconductor device manufacturing method); FIG. 2 is a cross-sectional view of a bipolar IC manufactured by a semiconductor device manufacturing method of the present invention; FIG. ) to FIG. 3B) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention. 1... Silicon substrate, 2... Epitaxial layer, 3
...Channel stop layer, 4...Embedded layer, 5...
・Oxide film isolation region, 6a...polysilicon layer for wiring,
7a...Resistance fi, 9a...Emitter layer, 10a
・Collector layer, lla...metal silicide layer, 12a
...Intermediate insulating film layer, 13a...Through hole hole, 1
4a... Second wiring layer, 15... Thin acid film layer, 16
...Nitride film layer, 17...Thin oxide film layer, A...Step, B...Polysilicon layer for wiring, C...Resistance contact portion. Procedural amendment December 23, 1980 Kazu Wakasugi, Commissioner of the Patent Office Failure 1, Indication of the case 1981 Patent Application No. 1352332, Title of invention Method for manufacturing semiconductor devices' 3, Person making the amendment Relationship to the case Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order: Showa year, month, day (self-motivated) 7, Contents of amendment as shown in attached sheet 2 Contents of amendment 1) Description, page 5, line 1 r 13 J k r 13 a
Correct it with J. 2) On page 5, line 1, "14" is corrected to r14aJ. It is corrected to "form and pace area as shown in FIG. 3(d)." 4) Delete "As shown in FIG. 3(b)" in lines 17 and 18 of the same line. 5) On page 9, line 9, ``Ning is possible'' is corrected to ``Ning is possible.'' 6) Correct line 9 of the second figure sound appendix of the drawing. 7) Correct the attached sheet of drawings Figures 3(e) to 3(b).

Claims (1)

[Claims] The semiconductor substrate is etched onto a platen, leaving a portion of the semiconductor substrate including the active region, and an oxide layer and a polycrystalline silicon layer are formed so as to be substantially flat with the surface of the platen, and the polycrystalline silicon layer is etched. A method of manufacturing a semiconductor device, comprising a step of selectively diffusing impurities.