JPS6027955B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece that can accurately correct the oscillation frequency error of a reference oscillator with a simple circuit configuration.

2. Description of the Related Art Electronic watches that use a stable crystal oscillator as a reference oscillator and perform timekeeping operations based on oscillation signals from the reference oscillator have been widely known.

In addition, among such electronic watches, there are also digital display types in which the time is displayed numerically, and in particular, digital displays whose display function is driven by electronic signals such as liquid crystals and LEDs are being considered. Electronic clocks have become well known. In such a digital display type electronic watch, the oscillation signal from the reference oscillator is divided and counted appropriately to generate a count signal corresponding to each time display unit such as "hour", "minute", "second", etc. This clock count signal controls the display drive of the numeric display function corresponding to each time unit to display the time.

In such electronic watches, by ensuring that the oscillation frequency of the reference oscillator is always set stably,
It has the great feature of always performing accurate timekeeping operations.

In this case, the purpose of stabilizing the oscillation frequency can be achieved, for example, by using a crystal oscillator, but in order to continue the timekeeping operation accurately, the oscillation frequency of the reference oscillator must be stabilized. It shall be set to the standard frequency set in conjunction with the counting circuitry. That is, it is necessary to correct the error between the oscillation frequency of the reference oscillator and the standard frequency. Therefore, in a reference oscillator that oscillates a signal that performs such a counting operation,
It is equipped with a mechanism for finely adjusting the oscillation frequency using a trimmer capacitor or the like, and the trimmer adjusts the oscillation frequency to match the reference frequency. However, for the reference oscillator,
Providing a trimmer adjustment mechanism as described above and manually adjusting it has the major disadvantage of increasing the amount of work in the watch assembly and adjustment process, and has a very negative impact on work efficiency and mass productivity. be.

In view of the above drawbacks, it is an object of the present invention to provide an electronic timepiece that accurately corrects the error between the oscillation frequency of a reference oscillator and the standard frequency using a simple circuit without adjusting the trimmer of the oscillator or the like. purpose.

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows its configuration, and numeral 11 is a shift register that constitutes a normal counting circuit for time display and various functional counting circuits such as a timer, world clock, alarm, and counter as needed. Yes, this shift register 11
In this case, an adder circuit 12, for example, a 4-bit shift memory section 13 including a correction circuit, is set in series so that the output signal of the shift memory section 13 is fed back to the input side of the shift register 11 via an OR circuit 14. It has a shift circulation circuit, and is dynamically shifted and driven by an oscillation signal from a reference oscillator 15 that performs stable oscillation operation, such as a crystal oscillator. (In this case, a frequency dividing circuit may be provided at the subsequent stage of the oscillator 15, and the output of this frequency dividing circuit may be used.) In this case, the dynamically driven shift register 11 has a frequency dividing circuit as shown in FIG. Cycle number storage unit 1 1a and “seconds” “1” sand J “minutes” “10
The unit storage units 11b, 11c, etc. corresponding to the time units such as "minute", "hour", etc. are set sequentially.In this case, "second", "1 Tochisuna", "minute", "10 minutes", " Each time unit, such as hour 1, only needs to be counted up to ``6'' to reach ``10'', so it is sufficient to configure each time unit with 4 bits, and the cycle number storage section stores 4 bits of digits into 2. It consists of 8 bits. That is, the information stored in the shift register 11 is configured such that one digit is composed of 4 bits, and the digits D1 and D2 are used to store the number of cycles in the cycle number storage section 11a, and the digits D3 and D4 are used to store "seconds" and "one inkstone". The unit count storage units 1 1b, 1 1c, . . . are set for each time unit. In addition, two correction value storage sections Q and 8 are set in the shift register 11 at predetermined positions. , DQ2, and DB1
, DB2). The 4-bit shift storage section 13, which is set in series in the shift register 1, detects count value information in units of digits and supplies it to the ROM 16.The decoder 17 also outputs necessary information in digits. It can be detected in units and the time can be displayed on a digital display device 18.

The oscillation signal of the reference oscillator 15 is transmitted to the bit counter 19.
is counted. This bit counter 19 is configured in 4 notation when one digit is 4 bits as described above, counts the bit order of the shift information output from the shift register 11, and sets each bit as "1" or "1". 2", "4
'', ``8'', and the bit order is used to count and generate timing signals J, , J2, J3, and IE. (In this case, JE=J4) The timing signal J, from the bit counter 19 is supplied to AND circuits 20 and 21, and the output signal synchronized with J, from the AND circuit 20 is added via an OR circuit 22. Addition information “11” is added to the circuit 12.
”. Further, the timing signal IE from the bit counter 19 is supplied to the AND circuit 23 together with the oscillation signal of the reference oscillator 15, and the digit pulse DP is taken out from the AND circuit 23, and the digit counter 24 is made to count. That is, this digit counter 24 counts the digits D, D2, etc. that are shifted from the shift register 11 to the shift storage section 13, and the digit information corresponding to the counted value is stored in the ROM 16 and the digits D, etc. ROM25 that obtains the timing signal of
supply to. In the ROM 16, the shift storage section 13
Compare the memorized count value with the digit information from the digit counter 24, and for example, when the memorized count value is "D3", the memorized count value is "
10", that is, when the "second" unit counter is counting "1 second", a signal is supplied to the OR circuit 26 and a clear command is issued to the shift storage section 13, and the "second" unit is counted.
Set the storage count value of the unit storage section to "0". The OR circuit 26 is also coupled with the carry signal from the adder circuit 12, and is driven by an oscillation signal, supplies it to the OR circuit 22 via a delay circuit 27 that delays by 1 bit, and then outputs the carry signal to the adder circuit 12. "1" is added to the unit storage section of the next most significant digit shifted from the shift register 11. In other words, as mentioned above, the count value of the unit counter for "seconds" is
When the carry condition for performing counting is reached, R
The OM16 detects this, clears the unit counter for that "second", and writes "
1" will be carried and added. This operation is performed entirely in the digits D1, D2, . . . that are set in the shift register 11 and perform the counting operation.
Here, the digit DI timing signal from the ROM 25 is added together with the AND circuit 2 timing T and the signal from the oscillator 15, and the AND circuit 20 outputs the first bit J of the digit D. Generates an output at the timing and sends "11" to the adder circuit 12.
Combined as information.

That is, the cycle number storage section 11 of the shift register 11
a is "11" for every shift cycle of this register 11, and this cycle number storage section 1
When the number of cycles in the shift register 1 corresponding to one second is counted in 1a, carry information "11" is combined with the digit D3 in units of "seconds". And oscillator 1
A shift register 11 that is shifted and driven by an oscillation clock signal of 5 performs a counting operation. here,
The number of storage bits including the circulation path of the shift register 11,
From the relationship with the oscillation frequency of the reference oscillator 15, assuming that the shift register 11 cycles 256 times in one second, the count value in the cycle number storage unit 11a becomes 256 times.
” When checking in ROM16, this RO
Generates an output signal from M16 and stores the cycle number storage section 11a.
At the same time, "1" is added to the digit D3, which is a unit counting section for "seconds", via the OR circuit 26, thereby creating a reference for the counting operation.

From the ROM 25, digits (DQ
I + DQ2) and (DB1 + DB2) timing signals, furthermore, the timing signals of the digit (DQI + DP1) specifying the lower digit parts of the storage sections Q and 8, and the timing signal corresponding to the last digit gray of the shift register 11. This De signal is supplied to an AND circuit 28 together with JE from the bit counter 19 and an oscillation signal from the oscillator 15, and an end pulse Ep is taken out from the AND circuit 28. Also, (D
QI + DQ2) and (DB1 + DB2) storage unit Q,
Timing signals corresponding to 8 are supplied to AND circuits 29 and 301, respectively.

The AND circuits 29 and 30 connect the output of the binary counter 31 and the inverter 32 to which this output is coupled.
The binary counter 31 is invertedly driven by the hourly pulse lp/h signal extracted from the ROM 16, which is gate-controlled by the outputs of the counters. That is, the AND circuits 29 and 30 output digits (DQI+D) every hour.
Output signals are obtained alternately at the timings of Q2) and (DB1 + DB2), and this power signal is supplied to the adder circuit 12 as a subtraction designation command (S) via the OR circuit 33. Further, the output signal from the OR circuit 33 is supplied to the AND circuit 34 together with the output signal from the shift register 11. When there is a numerical value in , an output signal indicating the presence of a number is generated and the flip-flop circuit 35 is set. The set output signal of the flip-flop circuit 35 is supplied to an AND circuit 36. This AND circuit 36 is further provided with a signal when a flip-flop circuit 37 is set, and this flip-flop circuit 37 is connected to the ROM1.
It is set by the pulse lp/m signal every minute obtained from the flip-flop circuit 35, and the RO
It is reset by the digit DI timing signal from M25. The output signal from the AND circuit 36 is read out from the delay circuit 3 for one cycle by the end pulse Ep.
8 to the AND circuits 21 and 39 as a gate signal. The AND circuit 21 receives the aforementioned signals J,
In addition, signals DQ1 and DB1 specifying the lower digits of the correction value storage units Q and 8 are supplied, and this AND circuit 2
The signal from 1 is supplied to the adder circuit 12 via an OR circuit 22. Further, the AND circuit 39 is supplied with the digit DI signal from the ROM 25 and the signal J8 from the bit counter 19, and its output signal is supplied to the shift storage section 13 as a preset command of "2". FIG. 3 shows a specific configuration example of the adder circuit 12 of the above embodiment, in which the shift output A from the shift register 11 and the output B from the OR circuit 22 are applied to AND circuits 40 and 41, respectively. An exclusive OR circuit 12a configured to gate control AND circuits 40 and 41 with inverters 42 and 43 supplied with signals B and A performs a bit addition operation, and outputs C via an OR circuit 46.
Try to get the following.

Further, the signals A and B are supplied to the AND circuit 44, and when both A and B are "1", a carry signal is obtained which is supplied to the upper digit as "11" information via the OR circuit 46. In this case, since a subtraction command (S female) is also given, the inverter 47 sets a condition that there is no subtraction command.
Further, the output of the AND circuit 41 is supplied to the AND circuit 48 together with the subtraction designation (S ship), and at this time, a borrow signal at the time of subtraction is obtained via the OR circuit 46.
FIG. 4 shows an example of the configuration of the shift storage section 13.
It has bit storage elements 49a to 949b, each of which is shifted and driven by an oscillation clock signal from the reference oscillator 15.

The input signals of the memory elements 49a to 49d are input to AND circuits 50a to 50d and OR circuit 51a, respectively.
51d in series, and the OR circuits 51a to 51d receive a 4-bit code signal "0010" from the code generation circuit 52 with a numerical value of "2".
are supplied respectively. Further, the clear command and preset command coupled from the outside are supplied to the OR circuit 53.
The output signal from this OR circuit 53 is supplied as a gate signal to the leading AND circuits 50a to 50d via an inverter 54. The preset command is further coupled to the code generation circuit 52 as a code generation command. That is, when a clear command is supplied, the gates of the first AND circuits 50a to 50d are closed, so that all "0" bits are transmitted to the memory elements 49a to 49d, and the bits corresponding to the clear command are The corresponding digit is set to "0".

Furthermore, when a preset command is supplied, the gates of the AND circuits 50a to 50d are similarly closed, and the contents of the memory elements 49a to 49d are preset to the code of numerical value "2" generated by the code generation circuit 52. and
When such a command does not exist, the information shifted from the adder circuit 12 is shifted and output as is.
That is, in the electronic timepiece configured as described above, the shift register 11 is shifted by the oscillation clock signal from the reference oscillator 15, and the stored information is circulated via the adder circuit 12 and the shift storage circuit 13. Ru. During this shift circulation, the digits of information shifted from the shift register 11 to the shift storage section 13 are counted by the digit counter 24, and the contents of the digits are detected by the ROM 16, and the digits forming each digit are counted by the digit counter 24. Bit output timing is counted and detected by a bit counter 19. Then, in each cycle of the shift circulation of information in the shift register 11, an output signal is generated corresponding to the digit DI of the cycle number storage section 11a from the ROM 25, and an output signal is generated from the AND circuit 20 in response to the leading bit J. A signal is generated to couple "1" information to the adder circuit 12. In this case, the subtraction command (S ship)
Therefore, the adder circuit 12 adds "1" to the cycle number storage section 11a for each shift cycle, and the number of cycles is counted and stored. Then, as described above, in the ROM 16, each unit storage section 11a, 11b is controlled by a carry condition signal obtained from the relationship between a digit and the count value of its corresponding digit.
, . . ., a counting operation is performed and the time is displayed on the display device 18. Here, if the oscillation frequency of the reference oscillator 15 accurately matches the standard frequency, accurate timekeeping operation can be performed only by the predetermined timekeeping operation as described above.

However, in reality, there is an error between the oscillation frequency of the reference oscillator 15 and the standard frequency, and in order to correct this error, conventional methods such as adjusting the trimmer capacitor have been taken. . On the other hand, in the electronic timepiece shown in the above embodiment, the oscillation frequency of the reference oscillator 15 is not adjusted, and the unit count storage unit 11b of the minimum unit "second" set in the shift register 1 is The carry generation conditions from the cycle number storage section 11a are changed so that the counting operation is ultimately executed accurately.

Specifically, for example, the reference oscillator 15 is set to be biased so that the oscillation frequency of the reference oscillator 15 has an error in a direction smaller than the standard frequency, and the cycle number storage unit 11a is
This control is performed to reduce the carry occurrence condition "256" to the upper digit.

In this case, if the above-mentioned carry occurrence conditions are corrected and changed all at once, the timing operation at that time will be unnatural.
is decreased by one every minute. That is, in this case, the shift register 11 performs "
``Pig = 256 cycles'', and in one minute there are ``(
The number of cycles per minute can be calculated as "(2 x 60)" or "(g x 60)" cycles.
0)-1)".

Therefore, 1 hour is [{(cross x 60) - 1} x + (g x 60) (6o - x
)] will be measured in cycles.

Here, since one hour is 60 minutes, it is 602xZO. Here, one cycle of the shift register 11 is 1/
Therefore, if x=1 in the above equation, the time equivalent to one cycle of the shift register is shortened in one hour, and the amount of correction is as shown in the equation below.

24 x concubine = 2 skins oo39o62 = o-o937 jobs/day =
2.8129 sand/month If x = 60, then 24 x back side = 5.531 jobs/day = 165-9379 sand/month, that is, 2. Time measurement correction is now performed for the current sand to 16 mother sand.

If it is a normal oscillator, the error in the oscillation frequency is very small and is well within this error range. Therefore, in the electronic timepiece shown in the above embodiment, the error of the oscillator is measured in advance, and the value of "x" is stored in the correction value storage section Q or 8 of the shift register 11 in the OR circuit 1.
4, the data is written and set together with information such as the time to be set in other parts of the shift register at that time, if necessary.

For example, if the value "x" is written in the correction value storage unit Q, the output of the binary counter 31 is set to "0" in the initial state.
Set it so that

When the counting operation is performed as described above in this state, the correction value storage section stores data from the ROM 25 at each shift circulation cycle of the shift register 11 as "DQI+DQ2" and "DB1+DB2" which specify the digit of 8. At this time, since the output of the binary counter 31 is "OJ", the AND circuit 29,
Through OR circuit 33, digits DQI and DQ2
A signal is generated in accordance with the timing when the signal is shifted out from the shift register 11.

The output signal from this OR circuit 33 is output from the adder circuit 1.
2, and when a numerical value exists in the correction value storage section Q of the shift register 11, the flip-flop circuit 35 is set by the output of the AND circuit 34. Further, the flip-flop circuit 37 is set by a signal generated from the ROM 16 every minute, and when both the flip-flop circuits 35 and 37 are set, an output is generated from the band circuit 36, and the next end signal is generated. In response to the generation of the pulse Ep, the delay circuit 38 provides a gate signal to the AND circuits 21 and 39 for one cycle. Therefore, a signal is applied from the AND circuit 21 to the adder circuit 12 via the OR circuit 22 at the timing of the first bit J of digit DQI in the next shift cycle of the shift register 11. At this time, a subtraction command is sent to the adder circuit 12 via the OR circuit 33 according to the digit DQI timing signal {
SUB} is given, so the adder circuit 12 subtracts "1" from the count stored value of the lower digit DQI of the correction value storage unit Q stored in the shift register 11. Also, an output is generated from the AND circuit 21 at the timing of DB1 that specifies another correction value storage section 8.

At this time, since there is no output from the OR circuit 33, the addition circuit 12 adds "1" to the correction value storage section 8. That is, the task is to subtract "1" from the storage section Q and add "1" to the storage section 8. Furthermore, the output of the delay circuit 38 provides a gate command to the AND circuit 39, and therefore the AND circuit 39
From then on, an output signal is generated at the timing of digit DI and in accordance with bit J2, and the shift storage section 13 is preset.

In this case, it is assumed that the lp'lm signal generated from the ROM 16 is generated in synchronization with the minute step, and corresponds to the signal from the flip-flop circuit 37 set by this lp/m signal. When the output signal is obtained from the AND circuit 39, the signal lp/m is generated, that is, one cycle after the step signal is sent from the cycle number storage section 11a to the upper side and cleared to "0". Therefore, the stored count value of the digit DI in the shift storage section 13 at that time is "1".

Therefore, with the signal from the AND circuit 39, the digit D
By presetting I to "2", the number of storage cycles in the shift register 13 is advanced by "one step" without counting the number of shift cycles in the shift register 13, and in effect, (
Goo 1) It is made to advance "seconds" in cycles. Then, the flip-flop circuits 35 and 37 are reset at the timing of this digit DI, and the above-mentioned cycle number correction operation is prohibited until the next signal lp/m is generated from the ROM 16. In other words, 1 minute is {(evening x 60) -
1}. This operation is repeated every minute while the correction value storage section Q has a numerical value, and the correction amount written in the storage section Q is
The number of cycles corresponding to "
x' is now counted and set. In other words, one hour during which the output of the binary counter 31 is "0" is [
The clock is measured in {zo x 60) - 1} x ten (evening x 60) (60 one x)] cycles. And then RO
For example, when an output signal of lp/h is generated from M16 at the beginning of the next hour, the binary counter 31 is inverted and its output becomes "1", so that the AND circuit 30' provides a gate signal. Become.

That is, the correction value storage section 8 of the shift register 11 is designated, and in the same manner as described above, "1" is subtracted from the storage section 8 every minute, and "1" is added to the storage section Q. As a result of this subtraction and addition, the shift storage section 13 presets the stored count value of the cycle number storage section 11a for the digit DI so that it advances by one step regardless of the shift cycle. The number of cycles x is subtracted from the set value in units of time, and this cycle number subtraction correction compensates for the error between the oscillation frequency of the reference oscillator 15 and the standard frequency, and continues accurate counting operation. The purpose is to ensure that

In the above embodiment, the reference oscillator 15 is biased toward the delay side,
The number of cycles in shift register 1 has been corrected to decrease, but this can be set in the complete opposite way to increase the number of cycles that measure 1 minute, or the correction of the number of cycles can be adjusted as well. It may be configured in this manner.

For this correction, the correction value "xJ-" may also be input corresponding to the measured value of the oscillation frequency of the reference oscillator 15, and the direction and amount of correction may be input when adjusting the time while the watch is in use. It may also be possible to detect and arbitrarily rewrite the number of cycles.In addition, the cycle number correction period was also shown in such a way that the number of cycles is corrected by one cycle every minute in units of one hour, but of course this period can be set arbitrarily; for example, the correction amount can be set on a daily basis.

The correction timing may also be set not every minute, but at timings obtained by dividing the correction unit time according to the correction amount x. In addition, it goes without saying that the present invention is not limited to the matters described above, and that various applications and changes can be made without departing from the gist of the present invention. As described above, according to the present invention, the timekeeping operation can be performed accurately by setting and controlling the correction value without finely adjusting the oscillation frequency of the reference oscillator by means such as trimmer adjustment. This not only improves the performance of electronic watches, but also greatly simplifies the adjustment work for oscillators, etc., and has a great effect on improving productivity.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram illustrating an electronic timepiece according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the storage contents of a shift register used in the above embodiment, and FIG. and FIG. 4 are diagrams showing configuration examples of the adder circuit and shift storage section of the above embodiment, respectively.

11...shift register, 12...addition circuit, 13
......Shift storage section, 15...Reference oscillator,
16, 25...ROM, 18...Display device, 19...Bit counter, 24...Digit counter, 31
...Binary counter, 35, 37...Flip-flop circuit.

Figure 2 Figure 4 Figure 3 figure rudder

Claims (1)

[Claims] 1. a reference oscillator, a counting means for counting signals based on the oscillation signal of the reference oscillator, a counting means for obtaining time information by incrementing the count value of the counting means each time it reaches a predetermined value; A second correction value storage section and a correction value m corresponding to an error between the oscillation frequency of the reference oscillator and the standard oscillation frequency per specified unit time are stored in either of the first and second correction value storage sections. means for writing and storing the correction value m in one of the units, means for specifying the first or second correction value storage section in which the correction value m is stored for each specified unit time; The above correction value m is calculated from the correction value storage unit No. 2 at each of m timings obtained by dividing the above unit time.
means for subtracting "1" until becomes zero and adding "1" to the other second or first correction value storage section; and subtraction and addition for the first and second correction value storage sections; An electronic timepiece characterized by comprising: a correction means for correcting the count value counted by the counting means each time the count value is counted by the counting means.