JPS6027917A - Output power control circuit - Google Patents

Abstract

PURPOSE:To perform wide-range output control while maintaining efficiency by providing an FET switch between the gate and drain of an FET amplifier, and switching the gate bias electric power of the switch and the gate bias electric power of the amplifier associatively. CONSTITUTION:An input voltage applied to an input terminal 1 is amplified by the FET amplifier 4 and also controlled by an FET switch 7 to control output electric power obtained at an output terminal 2. A resistance 8 utilizes the on resistance between the source and drain of the switch 7 and the gate bias voltage of the switch 7 is varied by a bias control circuit 11 to control its resistance value. Namely, the gain of the amplifier 4 is controlled by the gate bias voltage of the switch 7. Then, the gate bias voltage of the amplifier 4 is controlled by the circuit 11 associatively with the control over the resistance value so as to perform wide-range output control.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output power control circuit for an amplifier using field effect transistors (hereinafter referred to as FETs).

The schematic configuration of a conventional circuit of this type is shown in FIG. 1 and will be explained. In the figure, 1 is an input terminal to which an input voltage is applied;
2 is an output terminal from which output power is obtained, and 3 is a control terminal to which a control voltage is applied. Reference numeral 4 denotes an amplifier FET (hereinafter referred to as FET amplifier) consisting of an FET whose gate is supplied with the input voltage from input terminal 1, whose source side is grounded and whose drain side is connected to output terminal 2. It is also connected to a power source (VDD) 6 via a current control circuit 5.

In the circuit configured in this way, the current control circuit 5 is controlled by the control voltage from the control terminal 3, and in accordance with this, the drain current of the FET amplifier 4 is controlled, and the output power is controlled.

However, such a circuit has the following drawbacks.

That is, although a transistor is normally used in the current control circuit 5, the larger the power handled by the amplifier, the more a high-power control transistor is required. Furthermore, since the control transistor is interposed between the power supply and the amplifier, there is a drawback that a voltage drop occurs. therefore,
This poses a problem in designing amplifiers that require low-voltage power supply operation.

In view of the above points, the present invention was made to solve such problems and eliminate such drawbacks, and its purpose is to control output power over a wide range with a relatively simple configuration. Another object of the present invention is to provide an output power control circuit in which the control transistors can be constructed of relatively small-sized transistors and can be applied to monolithic implementation.

In order to achieve such an object, the present invention provides a FET switch that utilizes on-resistance between the gate and drain of an FET amplifier, and links the gate bias power of this FET switch with the gate bias voltage of the FET for the amplifier. By switching between the two, the output can be controlled over a wide range while maintaining the efficiency at a certain value.

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the output power control circuit according to the present invention.

In FIG. 2, the same reference numerals as in FIG. 1 indicate the osho parts, and 7 is an FET switch that is configured by an FET connected between the gate and drain of the FET amplifier 4 and that utilizes the on-resistance between the source and drain. And FET with
A negative feedback loop is provided, which includes a parallel resistor 8 for keeping the source and drain of the switch 7 at the same potential, and a capacitor 9 connected in series with the resistor 8 to cut off the DC bias. (10) is a choke coil for blocking AC signals, and 11 is a bias control circuit that generates the bias voltage necessary to perform specified output control based on the control signal input from the control terminal 3. For example, It consists of a switching circuit using diodes, transistors, etc. And this bias control circuit 1
One end of the FET amplifier 1 is connected to the control terminal 3, and the other end is connected to the connection point between the gate of the FET amplifier 4 and the input terminal 1 via the choke coil 10. 12 is a choke coil that blocks AC signals, and is connected to output terminal 2 and power supply (Vpo).
It is connected between the terminal 6 and the terminal 6. This output terminal 2 is connected to a connection point between the drain of the FET switch 7 and the drain of the FET amplifier 4.

13.14 is a gate bias output terminal of the bias control circuit 11, this gate bias output terminal 13 is connected to the gate of the FET amplifier 4 via the choke coil 10, and the gate bias output terminal 14 is connected to the gate of the FET switch 7. It is connected to the.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, the input voltage applied to the input terminal 1 is amplified by the FET amplifier 4 and controlled by the FET switch T, so that the output power obtained at the output terminal 2 is controlled.

The negative feedback resistance of the negative feedback loop utilizes the on-resistance between the source and drain of the FET switch 7, and by changing the gate bias voltage of the FET switch T by the bias control circuit 11, the resistance can be changed. Values can be controlled. That is, FET amplifier 4
The AC signal gain of can be controlled by the gate voltage of FET switch I.

In order to perform wide range output control including output cutoff, etc., the gate bias voltage of the FET amplifier 4 is controlled by the bias control circuit 11 in conjunction with the control of the negative feedback resistance value.

This makes it possible to control output power over a wide range while maintaining efficiency above a certain value.

The bias control circuit 11 is provided for this purpose, and as described above, the bias control circuit 11 controls the bias control circuit 11 according to the control signal input from the control terminal 3.
It generates the bias voltage necessary to perform specified output control, such as output power reduction, output power cutoff, etc.

FIG. 3 is a block diagram showing an embodiment of this bias control circuit 11. In this embodiment, in order to simplify the explanation, a case is shown in which the output ffj control is switched in two stages, but there is generally no essential difference even if the output ffj control is switched in n stages.

In FIG. 3, the same parts as in FIG. 2 are designated by the same reference numerals, and their explanation will be omitted. 15. IG and 17.1B each have two stages of required outputs, and the optimum bias pair (Vl, Vl') v (V 2 e V11
') is a bias input terminal that applies. 19, 20, 21, and 22 are analog switches, respectively, and these analog switches 19 to 22 are controlled by a control signal from the control terminal 3, and are configured to turn on and off. 23 is an inverter that inverts the control signal from the control terminal 3, and the inverted output of this inverter 23 is configured to be supplied to analog switches 21 and 22.

The control signal from the control terminal 3 is configured to be directly supplied to the analog switch 19.20, and each output terminal of the analog switch 19.21 is connected to the gate bias output terminal 13, and the analog switch 20 .22
Each output terminal of is connected to the gate bias output terminal 14.

Next, the operation of the embodiment shown in FIG. 3 will be explained.

First, it is assumed that the analog switches 19 to 22, which are turned on and off by control signals, are turned off when the control signal is H, and turned off when the control signal is L.

Next, when the control signal applied to the control terminal 3 is H,
Analog switches 21 and 22 are off, analog switches 19 and 20 are on, and gate bias output terminal 13
．． 14, voltages vl and vl' are generated, respectively. Further, when the control signal applied to the control terminal 3 is L, the analog switches 19 and 20 are turned off, and the analog switch 2
1.22 is on, the gate bias output terminal 13.
14, voltages vs, v,' are generated, respectively.

As is clear from the above description, according to the present invention, the gate bias voltage of the FET switch can be adjusted without using complicated means. By using a relatively simple circuit configuration in which the gate bias voltage of the FET amplifier and the gate bias voltage of the FET amplifier are switched in conjunction with each other, a wide range of output power can be controlled, and the drain current of the FET amplifier is not directly controlled yet. Due to the circuit configuration, FE for control
Since the T-switch can be constructed from relatively small-sized transistors, its practical effects are extremely large. Furthermore, by using the same type of transistor for the FET amplifier and the FET switch, it is extremely effective in that it can be applied to monolithic circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing an example of a conventional output power control circuit, FIG. 2 is a circuit diagram showing an embodiment of an output power control circuit according to the present invention, and FIG. 3 is a bias diagram in FIG. FIG. 2 is a block diagram of an embodiment showing a portion related to a control circuit; FIG. 41III fist FET amplifier, T1111@working FET
Switch, 811 resistor, 9... capacitor, 11Φ
...Bias control circuit.

Claims (1)

[Claims] A FET amplifier constituted by a field effect transistor whose gate is supplied with an input voltage and which takes out multiple outputs from its drain; and a field effect transistor connected between the gate and drain of the field effect transistor of the FET amplifier, and its source. - A bias supply resistor connected in parallel between the source and drain of the FET switch field effect transistor using the on-resistance between the drains and the capacitance of the bias supply reservoir connected in series with this resistor. Output power control characterized by comprising a negative feedback loop formed by a circuit consisting of an element, and a bias control circuit that supplies bias voltages to the gate terminal of the FET switch and the gate terminal of the FET amplifier, respectively. circuit.