JPH0794975A - High frequency hic module - Google Patents

Abstract

PURPOSE:To improve output control and efficiency and to attain easily operation by providing this high frequency HIC module with the 1st bias circuit for biasing the gate of a prescribed MOSFET based upon output control voltage and the 2nd bias circuit for biasing the gates of remaining MOSFETs based upon a fixed power supply and switching a route between the fixed power supply and the 2nd bias circuit. CONSTITUTION:When output control voltage VAPC is impressed to a control terminal 3, a bias circuit 13 imprsses bias voltage corresponding to the voltage VAPC to the gate of an initial MOSFET 9. At the time of impressing the voltage VAPC an analog switch 14 is turned on. Thereby a route from a power supply terminal 4 up to the input sides of bias circuits is turned to a conductive state and fixed power supply voltage VAPC is impressed from the terminal 4 to the input sides of the circuits 15, 16. The voltage is divided to the circuits 15, 16 and bias voltage corresponding to the divided voltage is impressed to the gates of intermediate and final MOSFETs 10, 11.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a high frequency HI for high power output.
The present invention relates to a C module, and more particularly to a high frequency HIC module using a MOS-FET as an active element.

[0002]

2. Description of the Related Art Conventionally, a high-power high-frequency HIC module using a MOS-FET has a high overall efficiency by utilizing the high gain and high-efficiency characteristics of a single MOS-FET. It can be said that it has high performance in combination with convenience in handling such as output control performed by a biased positive voltage (in the case of n-channel MOS-FET).

As a conventional high frequency HIC module, 3
FIG. 4 shows the circuit module configuration of the stage amplifier circuit.

The three-stage amplifier circuit shown in FIG.
an input terminal 101 for i, an output terminal 102 for output Po,
Control terminal 10 for output control voltage VAPC
3, and a power supply terminal 104 for the power supply voltage VDD. And, between the input terminal 101 and the output terminal 102, a high frequency impedance composed of a plurality of capacitors
Matching circuit (hereinafter simply referred to as high frequency circuit) 10
5, 106, 107 and 108 and three-stage amplifying n-channel MOS-FETs 109, 110 and 111 are alternately connected in cascade. These MOS-FETs 109-11
1, each gate is connected to the output side of the high frequency circuits 105 to 107, and each drain is connected to the high frequency circuits 106 to 1.
08 are respectively connected to the input side. Also, MOS
-Each drain of the FETs 109 to 111 is a power supply terminal 104
And the sources of the MOS-FETs 109 to 111 are grounded.

Further, a bias circuit 112 is connected to the control terminal 103. Bias circuit 112
Is composed of a plurality of resistors and capacitors, and generates a bias voltage according to the output control voltage VAPC to bias the gates of the MOS-FETs 109 to 111.

According to this circuit, the high frequency input Pi is impedance-matched by the high frequency circuits 105 to 108, is sequentially amplified by the MOS-FETs 109 to 111, and is output as the output Po from the output terminal 102.

[0007]

However, in the conventional three-stage amplifier circuit of the high frequency HIC module described above, the MO
Bias each gate of S-FET109-111,
Since the output control is performed by all the MOS-FETs 109 to 111, the output Po is the output control voltage VAPC as shown in the output control characteristic diagram of FIG.
In a part of the voltage range (2V to 3V), the voltage rises sharply and becomes saturated. Therefore, in this three-stage amplifier circuit, it is necessary to control the output Po within a narrow predetermined range (2V to 3V in the example) of the output control voltage VAPC, which is inconvenient in handling.

Further, the MOS-FET 111 in the output stage has a large gate width, and its threshold voltage Vth.
There is a risk that an excessively large bias current will flow due to variations in the above, and this has also been a cause of a decrease in efficiency ηT.

Further, the MOS-FETs 109 to 11 at the respective stages
When the bias voltage applied to 1 changes, the bias current changes and the input / output impedance of the element changes. As a result, since the matching characteristics of the high frequency circuits 105 to 107 are fixed, the matching is performed only in a part of the area and the mismatching occurs in the other areas. As a result, as shown in FIG. 5, the efficiency curve has a peak, which also contributes to inconvenience in handling.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to provide a high frequency HIC module which is excellent in output controllability, has improved efficiency, and is easy to handle. Is to provide.

[0011]

To achieve the above object, a feature of the present invention is that a plurality of MOSFETs connected to a fixed power source for amplifying and outputting an input signal and the above-mentioned MO transistors are provided.
A high-frequency HIC module comprising: a high-frequency impedance matching circuit provided between stages of SFETs; and a first bias circuit for biasing the gate of the MOSFET with a bias voltage generated based on an output control voltage. The bias circuit is configured to bias a gate of a predetermined MOSFET among the plurality of stages of MOSFETs based on the output control voltage, and the remaining MOSFETs other than the predetermined MOSFETs.
Is provided with a second bias circuit for biasing the gate of the above-mentioned gate on the basis of the fixed power supply, and a switch means for switching a path between the fixed power supply and the second bias circuit according to the output control voltage. .

[0012]

According to the above-mentioned structure, the first bias circuit generates the bias voltage based on the output control voltage, and the bias voltage biases the gate of the predetermined MOSFET. The second bias circuit generates a constant bias voltage based on the fixed power source when the switch means is in the ON state, and the remaining M is generated by this bias voltage.
The gate of the OSFET is biased. As a result, the output is controlled by changing and adjusting the bias voltage of only a predetermined MOSFET, so that the change in the output of the module with respect to the output control voltage does not become abrupt and is gentle. Further, since the gates of the remaining MOSFETs are biased with a constant bias voltage, the MO
The bias current flowing through the S-FET becomes constant, and this input / output impedance also becomes substantially constant. As a result, a mismatch with the high frequency circuit does not occur, and it is possible to prevent the efficiency from being extremely lowered.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a three-stage amplifier circuit which is a high frequency HIC module embodying the present invention, and FIG. 2 is a diagram showing a circuit module of the three-stage amplifier circuit.

This three-stage amplifier circuit has an input terminal 1 for high frequency input Pi, an output terminal 2 for output Po, a control terminal 3 for output control voltage VAPC, and a power supply voltage V
It has a power supply terminal 4 for DD. Further, high-frequency circuits 5, 6, 7, and 8 are provided between the input terminal 1 and the output terminal 2, and further, the first stage, the interruption, and the final stage are provided between the high-frequency circuits 5 to 8 respectively. 3 stages of amplifying n-channel MOS-FETs 9, 10, and 11 are provided. Here, as shown in FIG. 2, the high frequency circuits 5 to 8 have capacitors 5a, 5b and 5c and capacitors 6a and 6b, respectively.
, Capacitors 7a and 7b, and capacitors 8a and 8b,
And 8c.

The gates of the MOS-FETs 9 to 11 are connected to the output sides of the high frequency circuits 5 to 7, and the drains are connected to the input sides of the high frequency circuits 6 to 8 and the power supply terminal 4. ing. Also, MOS
-Each source of the FETs 9 to 11 is grounded, and between the power supply terminal 4 and the ground, as shown in FIG.
12b, 12c and 12d are provided.

Further, the gate of the MOS-FET 9 is connected to the control terminal 3 via the bias circuit 13,
The power supply terminal 4 is commonly connected to the input side of the bias circuits 15 and 16 via the analog switch 14. The output side of the bias circuits 15 and 16 is the MOS-F.
It is connected to each gate of the ETs 110 and 111, respectively. Here, as shown in FIG. 2, the bias circuit 13 is composed of resistors 13a, 13b and 13c and a capacitor 13d, and similarly, the bias circuit 15 has resistors 15a and 15c.
The bias circuit 16 includes resistors 16a, 16b, 16c and a capacitor 1b.
6d and.

The control terminal 3 is connected to the control side of the analog switch 14, so that the analog switch 14 is turned on based on the output control voltage VAPC applied to the control terminal 3 and fixed to the bias circuits 15 and 16. Power supply voltage VDD (eg 12.5V)
Are to be supplied.

Capacitors 17a and 17b are provided between the control terminal 3 and the ground, and a capacitor 18a is provided between the input side of the bias circuits 15 and 16 and the ground.
Is provided, and a capacitor 19a is provided between the input side of the analog switch 14 and the ground.

In the three-stage amplifier circuit of this embodiment having the above structure, the bias voltage of the middle-stage and last-stage MOS-FETs 10 and 11 of the three-stage amplifying MOS-FETs 9, 10 and 11 is constant and the first stage is constant. The output Po is controlled by changing and adjusting the bias voltage of only the MOS-FET 9.

That is, when the output control voltage VAPC is applied to the control terminal 3, the bias circuit 13
Applies a bias voltage corresponding to the output control voltage VAPC to the gate of the first stage MOS-FET 9 by voltage distribution of the resistors 13a, 13b, 13c. As a result, a bias current of, for example, 0 to 150 mA flows between the drain / source of the first-stage MOS-FET 9 according to the bias voltage.

On the other hand, when the output control voltage VAPC is applied, the analog switch 14 is turned on. As a result, the power supply terminal 4 and the input sides of the bias circuits 15 and 16 are brought into conduction, and the fixed power supply voltage VDD (12.5) is applied from the power supply terminal 4 to the input sides of the bias circuits 15 and 16.
V) is applied. As a result, the bias circuit 15 uses the resistors 15a, 15b, 15c to cause the bias circuit 16 to operate.
Are distributed by resistors 16a, 16b and 16c, respectively, and a bias voltage corresponding to the voltage distribution is applied to the middle-stage and final-stage MOS-
It is applied to the gates of the FETs 10 and 11.

As a result, a bias current of, for example, 200 mA flows between the drain / source of the middle MOS-FET 10, and a bias current of, for example, 600 mA flows between the drain / source of the final middle MOS-FET 11. At this time, the power supply voltage VDD is fixed,
Middle-stage and final-stage MOS-F when analog switch 14 is on
The bias current flowing through the ETs 10 and 11 is constant regardless of the output control voltage VAPC.

Since the bias current becomes constant in this way, the input and output impedances of the middle-stage and final-stage MOS-FETs 10 and 11 become substantially constant. In addition, the middle row,
High-frequency circuit 7 related to the final stage MOS-FETs 10 and 11,
By performing impedance matching of 8 for efficiency, the efficiency curve (shown in Fig. 5) does not sharply decrease with the increase of the output control voltage VAPC as in the conventional case, but in which range of the output control voltage VAPC. Even if there is, the characteristics of the element can be brought out.

As described above, in this embodiment, the first-stage MOS-
Since the output is controlled only by the FET 9, as is apparent from the output control characteristic diagram of this embodiment shown in FIG.
The steep rise of the output Po is eased (see the arrow in the figure), and it becomes unnecessary to control the output Po within a narrow predetermined range of the output control voltage VAPC.
The controllability of is improved.

Further, middle-stage and final-stage MOS-FETs 10 and 1
Since the bias voltage of 1 is supplied by the fixed power supply voltage VDD, the middle-stage and final-stage MOS-FETs 10 and 11
The bias current flowing through the input terminal becomes constant, and the input / output impedance becomes almost constant. As a result, mismatching with the high-frequency circuit does not occur, and the extreme decrease in efficiency at saturated output can be mitigated (see the arrow in the figure). And these advantages make the handling of this module convenient.

[0026]

As described above, the first bias circuit is the predetermined MOSF of the plurality of stages of MOSFETs.
The gate of ET is configured to be biased based on the output control voltage, and the remaining MO other than the predetermined MOSFET is
Since the second bias circuit for biasing the gate of the SFET based on the fixed power supply and the switch means for switching the path between the fixed power supply and the second bias circuit according to the output control voltage are provided, the output The steep rise of can be alleviated, and the controllability of the output is improved. Further, mismatching with the high frequency circuit does not occur, and the extreme decrease in efficiency can be mitigated. This makes the handling of this module convenient.

[Brief description of drawings]

FIG. 1 is a block diagram of a three-stage amplifier circuit embodying the present invention.

FIG. 2 is a diagram showing a circuit module of a three-stage amplifier circuit in the embodiment.

FIG. 3 is a diagram showing an output control characteristic of the embodiment.

FIG. 4 is a diagram showing a circuit module of a conventional three-stage amplifier circuit.

FIG. 5 is a diagram showing a conventional output control characteristic.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3 Control Terminal 5-8 High Frequency Circuit 9-11 n-Channel MOS-FET 13, 15, 16 Bias Circuit 14 Analog Switch Po Output VAPC Output Control Voltage Pi High Frequency Input

Claims (1)

[Claims] 1. A plurality of MOSFETs connected to a fixed power source for amplifying and outputting an input signal, and each of the MOSFETs.
A high frequency impedance matching circuit provided between the stages of T and the MOSF based on the output control voltage.
In a high frequency HIC module including a first bias circuit for biasing a gate of ET, the first bias circuit biases a gate of a predetermined MOSFET among the plurality of stages of MOSFETs based on the output control voltage. The predetermined MOSF
A second bias circuit for biasing the gates of the remaining MOSFETs other than ET based on the fixed power supply; and a switch means for switching the path between the fixed power supply and the second bias circuit according to the output control voltage. A high-frequency HIC module characterized by being provided with.